Granted Patent B2

US 9,209,081 · App. 13/773,603 · Granted Dec 8, 2015

Abstract

Claims (30)

1. A semiconductor grid array package, comprising:

a first housing member with a cavity therein, the cavity having a cavity floor at least partially surrounded by cavity walls;

a semiconductor die having a mounting surface and an opposite interface surface with external connection pads, wherein the mounting surface is affixed to the cavity floor;

a second housing member molded to the first housing member and covering at least the interface surface;

a plurality of electrically conductive runners mounted to an external surface of the second housing member, the runners having a wire contacting area and an external connector contacting area;

bond wires selectively bonded to the external connection pads of the semiconductor die and the wire contacting areas of the runners, wherein the bond wires include at least one bridging wire that has a first end bonded to a first one of the external connection pads, an opposite second end bonded to a second one of the external connection pads, and an intermediate section exposed at a same plane of an upper surface of the second housing member and connected to the wire contacting area, wherein part of the intermediate section is removed; and

external electrical connectors mounted to the external connector contacting areas of the runners.

2. The semiconductor grid array package of claim 1 , wherein the bridging wire is connected to the wire contacting area by a sputter coating that partially forms the runners.

3. The semiconductor grid array package of claim 1 , wherein the bond wires include a stump wire with a first end bonded to one of the external connection pads and an opposite second end connected to the wire contacting area of a selected one of the runners.

4. The semiconductor grid array package of claim 3 , wherein the opposite second end of the stump wire is connected to the wire contacting area by a sputter coating that partially forms the runners.

5. The semiconductor grid array package of claim 1 , wherein the first housing member is part of a pre-molded die carrier that supports the semiconductor die during wire bonding of the bond wires to the external connection pads.

6. The semiconductor grid array package of claim 1 , wherein the semiconductor die is a first semiconductor die and there is a second semiconductor die with a second semiconductor die mounting surface affixed to the interface surface of the first semiconductor die.

7. The semiconductor grid array package of claim 6 , wherein the bond wires selectively interconnect external connection pads of the first semiconductor die to external connection pads of the second semiconductor die.

8. The semiconductor grid array package of claim 7 , wherein the bond wires selectively connect the external connection pads of the second semiconductor die to the wire contacting areas of the runners.

9. The semiconductor grid array package of claim 6 , further comprising a third semiconductor die affixed to the cavity floor.

10. A method for assembling a grid array package, comprising:

providing a die carrier with a cavity therein, the die carrier providing a first housing member and wherein the cavity has a cavity floor at least partially surrounded by cavity walls;

placing a semiconductor die in the cavity, the semiconductor die having a mounting surface and an opposite interface surface with external connection pads, wherein the mounting surface is fixed to the cavity floor;

selectively bonding bond wires to the external connection pads, wherein the bond wires include at least one bridging wire that has a first end bonded to a first one of the external connection pads, and an opposite second end bonded to a second one of the external connection pads;

molding a second housing member to the die carrier so that the second housing member covers the interface surface and lengths of the bond wires;

depositing a plurality of electrically conductive runners to an external surface of the second housing member, the runners having a wire contacting area and an external connector contacting area, wherein the bond wires are selectively connected to a said wire contacting area, wherein an intermediate section of the bridging wire is exposed at a same plane of an upper surface of the second housing member and connected to the wire contacting area, wherein said depositing includes removing part of the intermediate section; and

mounting external electrical connectors to a respective external connector contacting area.

11. The method for assembling a grid array package of claim 10 , wherein the depositing includes:

grinding the second housing member to expose a wire contacting area of the bond wires; and

partially forming the runners by selectively depositing sputter coatings on the external surface.

12. The method for assembling a grid array package of claim 11 , wherein the depositing includes plating the sputter coatings with metallic based conductors to thereby provide the electrically conductive runners.

13. The method for assembling a grid array package of claim 12 , wherein the depositing further includes selectively depositing a dielectric covering over parts of the electrically conductive runners, wherein the dielectric covering has apertures therein that expose the external connector contacting area of the runners.

14. The method for assembling a grid array package of claim 11 , wherein the die carrier is integrally molded into a sheet of die carriers and the method further includes singulating the die carrier from the sheet of die carriers.

15. The method for assembling a grid array package of claim 14 , wherein the die carrier and second housing member form a housing of the grid array package.

16. The method for assembling a grid array package of claim 10 , wherein the semiconductor die is a first semiconductor die and the placing further includes affixing a second semiconductor die with a second semiconductor die mounting surface to the interface surface of the first semiconductor die.

Assignments (23)