THREAD-SUSPENDING EXECUTION BARRIER
An energy-efficient execution barrier for parallel processing is provided. The execution barrier associates a thread-execution bit with each hardware-supported thread. The energy-efficient execution barrier utilizes a per-processor or per-chip bit vector register, having, for example, one bit per possible thread. A bit enables or disables the execution of its corresponding thread. A process starts by forking threads and enabling them in the bit vector register. When a thread arrives at the barrier/rendezvous, the thread disables its own bit and therefore suspends thread execution. When a distinguished thread arrives at the barrier, it waits (e.g., spinlocks) until all the threads needed for the rendezvous are disabled. The distinguished thread (or an automatic thread re-enable mechanism) then atomically sets all threads bits in the bit vector register to enabled, and the threads perform any appropriate sync operations and continue.
1 . A processing apparatus comprising:
a processing structure configured to execute program code using a plurality of threads;
a bit register including a plurality of bits, wherein during operation each thread being executed by the processing structure corresponds to a bit of the plurality of bits, wherein each of the plurality of threads can change its corresponding bit from a first state to a second state, wherein the execution of the program code of each of the plurality of threads is suspended when its corresponding bit is in the second state; and
a thread re-enablement entity for changing the corresponding bits for the plurality of bits from the second state to the first state to re-enable execution of the program code of the plurality of threads.
2 . The processing apparatus of claim 1 wherein the thread re-enablement entity is a distinguished thread executed on the processing structure.
3 . The processing apparatus of claim 2 wherein the distinguished thread waits for the corresponding bits for each of the plurality of bits to attain the second state before changing the corresponding bits from the second state to the first state.
4 . The processing apparatus of claim 2 wherein the program code of the distinguished thread is executed on a first processor core and the distinguished thread interacts with a second distinguished thread of a second processor core.
5 . The processing apparatus of claim 1 wherein the thread re-enablement entity is a thread re-enablement mechanism responsive to the corresponding bits for each of the plurality of threads attaining the second state.
6 . The processing apparatus of claim 5 wherein the thread re-enablement mechanism comprises digital logic gates.
7 . The processing apparatus of claim 1 further comprising:
a thread mask for masking off additional threads, wherein the bit register comprises additional bits respectively corresponding to the additional threads.
8 . (canceled)
9 . In a processor device, a method comprising:
executing pre-execution barrier computations based upon program code of a thread, wherein the thread is to stop executing the program code in response to reaching an execution barrier;
changing a thread enable status register bit from a first state to a second state upon the thread reaching the execution barrier;
suspending program code execution by the thread until the thread enable status register bit returns to the first state; and
executing post-barrier computations in response to the thread enable status bit register bit having returned to the first state.
10 . The method of claim 9 further comprising:
executing pre-barrier synchronization operations to ensure that prior memory operations have completed.
11 . (canceled)
12 . The method of claim 9 further comprising:
changing at least a second thread enable status register bit from the first state to the second state upon at least a second thread of a plurality of threads reaching the execution barrier, wherein a plurality of thread enable status register bits correspond, respectively, to the plurality of threads; and
suspending thread execution of the second program code of the second thread until the second thread enable status register bit returns to the first state, wherein the plurality of thread enable status register bits return to the first state in response to the plurality of thread enable status register bits having been changed from the first state to the second state.
13 . The method of claim 9 further comprising:
returning, by execution of a supervisory operation of a distinguished thread, the plurality of thread enable status register bits to the first state.
14 . The method of claim 9 further comprising:
returning, by operation of a thread re-enablement mechanism, the plurality of thread enable status register bits to the first state.
15 . In a processor device, a method comprising:
suspending a first execution of first program code of a first thread by entering a quiescent state upon the first execution of the first thread reaching a first execution barrier;
suspending a second execution of second program code of a second thread by entering the quiescent state upon the second execution of the second thread reaching a second execution barrier;
detecting when the first execution of the first program code of the first thread and the second execution of the second program code of the second thread have been suspended by entering the quiescent state; and
re-enabling the first execution of the first program code of the first thread by entering an active state and the second execution of the second program code of the second thread by entering the active state.
16 . The method of claim 15 wherein the re-enabling comprises:
re-enabling by a first supervisory operation of a distinguished thread the first execution of the first program code of the first thread by entering the active state and the second execution of the second program code of the second thread by entering the active state.
17 . The method of claim 16 wherein the detecting comprises:
detecting by a second supervisory operation of the distinguished thread when the first execution and the second execution have been suspended by entering the quiescent state while the distinguished thread remains in the active state.
18 . The method of claim 17 wherein the detecting by second supervisory operation of the distinguished thread comprises:
spinlocking by the second supervisory operation of the distinguished thread while the quiescent state of at least one of the first thread and the second thread prevents the at least one of the first thread and the second thread from spinlocking.
19 . The method of claim 16 further comprising:
engaging by the distinguished thread in a execution barrier protocol with another distinguished thread of another processor device.
20 . The method of claim 16 further comprising:
placing the distinguished thread in a low-power state; and
restoring the distinguished thread from the low-power state.
21 . The method of claim 15 wherein the re-enabling comprises:
re-enabling by a thread re-enablement mechanism the first execution of the first program code of the first thread and the second execution of the second program code of the second thread.
22 . The method of claim 15 further comprising:
applying a thread mask to specify the first thread and the second thread as being subject to the detecting and re-enabling.