Non-volatile memory (NVM) with word line driver/decoder using a charge pump voltage
A word line driver that includes a pull up transistor for biasing a node of a stack of transistors that are located between a high supply voltage terminal and a low supply voltage terminal. The node is biased at a voltage that is between the high supply voltage and the low supply voltage. The stack of transistors includes a stack of decode transistors and a cascode transistor. The cascode transistor is located between the node and a second node of the stack that is coupled to an inverting circuit.
1. A word line driver comprising:
a first stack of transistors, the first stack including:
a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;
a cascode transistor having a first current electrode connected to the first node, the cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;
a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the cascode transistor;
a pull up transistor having a first current electrode coupled to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode coupled to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage; and
an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node;
wherein the plurality of decode transistors are characterized as lower voltage transistors; and
wherein the third transistor is characterized as a higher voltage transistor.
2. The word line driver of claim 1 wherein the source voltage terminal is connected to the third supply voltage terminal and supplies the third supply voltage.
3. The word line driver of claim 1 wherein the output of the inverting circuit is coupled to a word line.
4. The word line driver of claim 1 wherein the decode transistors and the cascode transistor are characterized as N-channel transistors and the pull up transistor and the third transistor are characterized as P-channel transistors.
5. The word line driver of claim 1 wherein:
during operation, the first node operates at a voltage in a first range between a voltage of the first voltage supply terminal and a voltage of the third voltage supply terminal; and
during operation, the second node operates at a voltage in a second range between a voltage of the first voltage supply terminal and a voltage of the second voltage supply terminal.
6. The word line driver of claim 1 wherein the control electrode of the pull up transistor is connected to a control electrode of a top transistor in the stack of the plurality of decode transistors.
7. The word line driver of claim 1 wherein the inverting circuit includes an N-channel transistor and a P-channel transistor each including a control electrode connected to the input of the inverting circuit, wherein a first current electrode of the N-channel transistor is connected to a first current electrode of the P-channel transistor, wherein the N-channel transistor and the P-channel transistor are characterized as higher voltage transistors.
8. The word line driver of claim 1 wherein during operation, the output of the inverting circuit operates at a voltage in a third range at least between a voltage of the first voltage supply terminal and a voltage of the second voltage supply terminal.
9. The word line driver of claim 1 wherein the first stack of transistors further includes a fourth transistor located in the first stack between the second node and the cascode transistor wherein the fourth transistor is characterized as a higher voltage transistor.
10. The word line driver of claim 9 wherein the cascode transistor is characterized as a lower voltage transistor.
11. The word line driver of claim 9 wherein the cascode transistor and the fourth transistor are N-channel transistors.
12. The word line driver of claim 1 wherein the cascode transistor is characterized as a lower voltage transistor.
13. The word line driver of claim 1 wherein the cascode transistor is characterized as a higher voltage transistor.
14. The word line driver of claim 1 wherein during operation, the pull up transistor biases the first node at the voltage of the third supply voltage terminal when the plurality of decode signals are at non asserted levels.
15. The word line driver of claim 1 wherein the first node is at a voltage of the third supply voltage terminal and the second node is at a voltage of the second supply voltage terminal when the plurality of decode signals are at non asserted levels.
16. The word line driver of claim 1 wherein the third transistor includes a control electrode that is connected to a second source voltage terminal for providing a second source voltage, wherein the second source voltage is less than the second supply voltage so as to limit an amount of current flowing through the transistor when conductive.
17. The word line driver of claim 1 wherein the pull up transistor is characterized as a lower voltage transistor.
18. A memory comprising the word line driver of claim 1 , the memory further comprising:
an address decoder, the address decoder providing the decode signals;
an array of memory cells; and
a plurality of word lines, wherein the word line driver is coupled to provide a word line signal on a word line of the plurality of word lines, wherein the word line is coupled to a subset of memory cells of the array.
19. The memory of claim 18 further comprising:
a charge pump including an output coupled to the second supply voltage terminal.
20. A word line driver comprising:
a first stack of transistors, the first stack including:
a plurality of decode transistors coupled in a stack between a first node of the first stack of transistors and a first voltage supply terminal for supplying a first supply voltage, wherein each of the decode transistors includes a control electrode to receive a decode signal of a plurality of decode signals;
a first cascode transistor having a first current electrode connected to the first node, the first cascode transistor including a control electrode coupled to a source voltage terminal for providing a source voltage;
a second cascode transistor having a first current electrode coupled to a second current electrode of the first cascode transistor; and
a third transistor, a first current electrode of the third transistor is connected to a second node of the first stack of transistors, wherein the second current electrode of the third transistor is coupled to a second supply voltage terminal for supplying a second supply voltage, the second node is coupled to a second current electrode of the second cascode transistor;
a pull up transistor having a first current electrode connected to the first node, a second current electrode coupled to a third supply voltage terminal for supplying a third supply voltage, and a control electrode connected to a decode signal of the plurality of decode signals, wherein the second supply voltage is higher than the first supply voltage and higher than the third supply voltage, wherein the third supply voltage is higher than the first supply voltage; and
an inverting circuit including an input and an output, the input is coupled to the second node, wherein inverting circuit provides at its output, and inverted logic state of the second node;
wherein the plurality of decode transistors, the first cascode transistor, and the pull up transistor are characterized as lower voltage transistors;
wherein the third transistor and the second cascode transistor are characterized as higher voltage transistors; and
wherein the plurality of decode transistors, the first cascode transistor, and the second cascode transistor are N-channel transistors, and the pull up transistor and the third transistor are P-channel transistors.