Method of forming a semiconductor device having a dielectric layer with high dielectric constant
View Patent ↗A method for forming a semiconductor device ( 10 ) creates a dielectric layer ( 18 ) with high dielectric constant. An interfacial layer ( 14 ) is formed over a semiconductor substrate ( 12 ). A dielectric layer ( 16 ) is formed over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K). The dielectric layer is thinned, such as by etching or chemical mechanical polishing, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning. In one form, the method is used to form a transistor having a gate electrode layer formed over the thinned dielectric layer and source/drain diffusions ( 24, 26 ) within the semiconductor substrate.
1. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate;
forming an interfacial layer over the semiconductor substrate;
forming a dielectric layer over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K);
thinning the dielectric layer to form a thinned dielectric layer, wherein a thickness of the thinned dielectric layer is less than a thickness of the dielectric layer prior to thinning;
forming a conductive layer overlying the thinned dielectric layer; and
patterning and etching the interfacial layer, the thinned dielectric layer, and the conductive layer to form a gate stack for a semiconductor device.
2. The method of claim 1 , wherein a thickness of the interfacial layer does not substantially change during the forming of the dielectric layer.
3. The method of claim 1 , wherein the forming the dielectric layer uses at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-on deposition, plating, electroless plating or oxidation of a metal or metal composites.
4. The method of claim 1 , wherein the interfacial layer has a thickness in a range of approximately 0.3 to 1.2 nanometers.
5. The method of claim 1 , wherein the thickness of the dielectric layer prior to thinning is at least approximately 5 nanometers.
6. The method of claim 1 , wherein the thickness of the dielectric layer prior to thinning is at least approximately 10 nanometers.
7. The method of claim 1 , wherein the thickness of the thinned dielectric layer is at most 3 nanometers.
8. The method of claim 1 , wherein the dielectric layer comprises at least one of a metal oxide, a metal silicate, a metal aluminate, a metal oxynitride or a metal silicon oxynitride.
9. The method of claim 8 , wherein during the forming of the dielectric layer, metal from the dielectric layer penetrates into at least a portion of the interfacial layer.
10. The method of claim 1 , wherein the thinned dielectric layer comprises a polycrystalline metal oxide.
11. The method of claim 1 , further comprising performing a thermal treatment before or after the thinning the dielectric layer.
12. The method of claim 1 , wherein forming the interfacial layer comprises at least one of a chemical oxide, a thermally grown oxide, or a deposited oxide.
13. The method of claim 1 , wherein forming the interfacial layer comprises:
thermally growing an oxide layer; and
etching the oxide layer to form the interfacial layer.
14. The method of claim 1 , wherein the interfacial layer comprises an oxide of the semiconductor substrate.
15. The method of claim 14 , wherein after the forming the dielectric layer, the interfacial layer comprises the oxide of the semiconductor substrate and a metal from the dielectric layer.
16. The method of claim 1 , wherein the thinning the dielectric layer comprises performing at least one of a wet etch, a dry etch or chemical mechanical polishing (CMP) of the dielectric layer.
17. The method of claim 1 , further comprising:
patterning the interfacial layer, the thinned dielectric layer, and the gate electrode layer to form a substantially completed semiconductor device.
18. A method for forming a semiconductor device, comprising:
providing a silicon substrate;
forming an interfacial layer over the silicon substrate;
forming a hafnium oxide layer over the interfacial layer;
etching the hafnium oxide layer to thin the hafnium oxide layer and form a thinned hafnium oxide layers;
forming a conductive layer overlying the thinned hafnium oxide layer; and
patterning and etching the interfacial layer, the thinned hafnium oxide layer, and the conductive layer to form a gate stack for a semiconductor device.
19. The method of claim 18 , wherein a thickness of the interfacial layer does not substantially change during the forming the hafnium oxide.
20. The method of claim 18 , wherein prior to the forming the hafnium oxide layer, the interfacial layer comprises silicon dioxide and after the forming the hafnium oxide layer, the interfacial layer comprises a metal silicate.
21. The method of claim 18 , forming the hafnium oxide layer comprises forming a polycrystalline hafnium oxide layer.
22. The method of claim 18 , wherein the etching the hafnium oxide layer comprises using hydrochloric acid or phosphoric acid.
23. The method of claim 18 , wherein prior to the etching the hafnium oxide layer, the hafnium oxide layer has a thickness of at least approximately 5 nanometers, and after the etching the hafnium oxide layer, the thinned hafnium oxide layer has a thickness of at most approximately 3 nanometers.
24. The method of claim 18 , wherein the interfacial layer has a thickness of in a range of approximately 0.3 to 1.2 nanometers.
25. The method of claim 18 , further comprising performing a thermal treatment before or after the etching the hafnium oxide layer.
26. The method of claim 18 , wherein forming the hafnium oxide layer uses at least one of atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), spin-on or plating.
27. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate;
forming an interfacial layer over the semiconductor substrate, the interfacial layer having a thickness in a range of approximately 0.3 to 1.2 nanometers;
forming a dielectric layer over the interfacial layer, wherein the dielectric layer has a high dielectric constant (K) and a thickness of at least approximately 5 nanometers;
thinning the dielectric layer to a thickness of at most approximately 3 nanometers to form a thinned dielectric layer,
forming a conductive layer overlying the thinned dielectric layer; and
patterning and etching the interfacial layer, the thinned dielectric layer, and the conductive layer to form a gate stack for a semiconductor device.
28. The method of claim 27 , wherein the thickness of the dielectric layer prior to the thinning is at least approximately 10 nanometers.
29. The method of claim 27 , wherein the thickness of the dielectric layer prior to the thinning is at least approximately 20 nanometers.
30. The method of claim 27 , wherein a thickness of the interfacial layer does not substantially change during the forming the dielectric layer.
31. The method of claim 27 , wherein the dielectric layer comprises at least one of a metal oxide, a metal silicate, a metal aluminate, a metal oxynitride or a metal silicon oxynitride.
32. The method of claim 31 , wherein during the forming of the dielectric layer, metal from the dielectric layer penetrates into at least a portion of the interfacial layer.
33. The method of claim 27 , wherein the thinned dielectric layer comprises a polycrystalline metal oxide.
34. The method of claim 27 , wherein the interfacial layer comprises an oxide of the semiconductor substrate.
35. The method of claim 34 , wherein after formation of the dielectric layer, the interfacial layer comprises the oxide of the semiconductor substrate and a metal from the dielectric layer.
36. The method of claim 27 , wherein thinning of the dielectric layer comprises performing at least one of a wet etch, a dry etch or chemical mechanical polishing of the dielectric layer.