Tunable antifuse elements
View Patent ↗A tunable antifuse element ( 102, 202, 204, 504, 952 ) includes a substrate material ( 101 ) having an active area ( 106 ) formed in a surface, a gate electrode ( 104 ) having at least a portion positioned above the active area ( 106 ), and a dielectric layer ( 110 ) disposed between the gate electrode ( 104 ) and the active area ( 106 ). The dielectric layer ( 110 ) includes a tunable stepped structure ( 127 ). During operation, a voltage applied between the gate electrode ( 104 ) and the active area ( 106 ) creates a current path through the dielectric layer ( 110 ) and a rupture of the dielectric layer ( 110 ) in a rupture region ( 130 ). The dielectric layer ( 110 ) is tunable by varying the stepped layer thicknesses and the geometry of the layer.
1. A tunable antifuse element comprising:
a substrate material having a first stepped structure defining a high side of the substrate and a low side of the substrate, wherein the first stepped structure has a first slope;
an active area formed in a surface of the substrate material;
a gate electrode having at least a portion positioned above the active area; and
a tunable dielectric layer including a second stepped structure located directly over the first stepped structure, wherein the second stepped structure has a second slope with a same slope direction but a different slope magnitude from the first slope, and the tunable dielectric layer is disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the tunable dielectric layer and a rupture of the tunable dielectric layer in a rupture region, wherein the tunable dielectric layer has a thick oxide portion over the high side of the substrate and a thin oxide portion over the low side of the substrate, and the rupture region is located along a transition area between the thick oxide portion and the thin oxide portion.
2. A tunable antifuse element as claimed in claim 1 , wherein the tunable antifuse element is a capacitor.
3. A tunable antifuse element as claimed in claim 1 , wherein the substrate material is a semiconductor material.
4. A tunable antifuse element as claimed in claim 2 , wherein the active area comprises an electrically conductive doped region.
5. A tunable antifuse element as claimed in claim 1 , wherein the tunable dielectric layer is a tunable gate oxide layer.
6. A tunable antifuse element as claimed in claim 5 , wherein the thin oxide portion has a thickness T 1 and the thick oxide portion has a thickness T 2 , wherein T 1 is less than T 2 , and the stepped structure is defined by a thickness variation between the thin oxide portion and the thick oxide portion.
7. A tunable antifuse element as claimed in claim 6 , wherein the stepped structure includes a plurality of thick oxide portions and at least one thin oxide portion.
8. A tunable antifuse element as claimed in claim 6 , wherein the stepped structure includes a plurality of thin oxide portions and at least one thick oxide portion.
9. A tunable antifuse array comprising:
a plurality of bit cells, each of the plurality of bit cells comprising at least one tunable antifuse element,
wherein each of the at least one tunable antifuse elements is comprised of:
a substrate material having a first stepped structure defining a high side of the substrate and a low side of the substrate, wherein the first stepped structure has a first slope;
an active area formed in a surface of the substrate material;
a gate electrode having at least a portion positioned above the active area; and
a tunable dielectric layer including a second stepped structure located directly over the first stepped structure, wherein the second stepped structure has a second slope with a same slope direction but a greater slope magnitude than the first slope, and the tunable dielectric layer is disposed between the gate electrode and the active area such that a voltage between the gate electrode and the active area creates a current path through the tunable dielectric layer and a rupture of the tunable dielectric layer in a rupture region, wherein the tunable dielectric layer has a thick oxide portion over the high side of the substrate and a thin oxide portion over the low side of the substrate, and the rupture region is located along a transition area between the thick oxide portion and the thin oxide portion.
10. A tunable antifuse array as claimed in claim 9 , further including at least one select transistor.
11. A tunable antifuse array as claimed in claim 9 , wherein the at least one tunable antifuse element is a capacitor.
12. A tunable antifuse array as claimed in claim 9 , wherein the thin oxide portion has a thickness T 1 and the thick oxide portion has a thickness T 2 , wherein T 1 is less than T 2 , and the stepped structure is defined by a thickness variation between the thin oxide portion and the thick oxide portion.
13. A tunable antifuse array as claimed in claim 12 , wherein the stepped structure includes a plurality of thin oxide portions and at least one thick oxide portion.
14. An antifuse element comprising:
a substrate having a first gradual step structure defining a high side of the substrate and a low side of the substrate;
an active area formed within the substrate;
a gate oxide formed over the first gradual step structure, wherein the gate oxide has a second gradual step structure located directly over the first gradual step structure, the first gradual step structure has a first slope, the second gradual step structure has a second slope, and the second slope has a same slope direction but a greater slope magnitude than the first slope, wherein the gate oxide has a thick oxide portion over the high side of the substrate and a thin oxide portion over the low side of the substrate; and
a gate electrode formed over the gate oxide such that the gate oxide, the gate electrode, and the active area of the substrate form a rupture region having an actual breakdown voltage substantially equal to a target breakdown voltage, and the rupture region is located along a transition area between the thick oxide portion and the thin oxide portion in proximity to the first gradual step structure and the second gradual step structure.
15. The antifuse element of claim 14 , wherein the active area comprises a heavily doped diffusion contact.
16. The antifuse element of claim 14 , wherein the gate oxide has a submicron minimum thickness, and a maximum thickness that is greater than the minimum thickness.
17. The antifuse element of claim 14 , wherein the gate electrode is formed from polysilicon.
18. The antifuse element of claim 14 , wherein the antifuse element forms a portion of a dual gate metal oxide field effect transistor (MOSFET).