Fabrication of three dimensional integrated circuit employing multiple die panels
View Patent ↗A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M×N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M×N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.
1. A method of assembling of an electronic device, comprising:
testing a first wafer comprising a plurality of first sets of dies to identify the location of functional first sets of dies within the first wafer;
dividing the first wafer into a plurality of first sets of multiple-die panels, wherein each panel includes an M×N array of the first die wherein each panel of the first set of multiple-die panels includes a plurality of first sets of dies;
categorizing the plurality of first sets of multiple-die panels into a first plurality of bins based on a predetermined yield pattern associated with the first wafer;
bonding the first set of multiple-die panels to panel sites of a second wafer to form a panel stack, wherein the panel sites include an M×N array of second sets of dies, wherein bonding includes testing and categorizing the panel sites of the second wafer into a second plurality of bins based on the predetermined yield pattern associated with the first wafer and wherein the bonding step further includes bonding the first set of multiple-die panels to the panel sites of the second wafer selectively to minimize functional mismatches; and
sawing the panel stack into a set of electronic devices, each electronic device comprising a first die bonded to a second die.
2. The method of claim 1 , wherein dividing the first wafer comprises dividing the first wafer according to a static mapping of panels in the first wafer.
3. The method of claim 1 , wherein dividing the first wafer comprises dividing the first wafer to maximize the number of panels having a panel yield exceeding a specified threshold wherein a panel yield indicates the number of functional first die in a panel.
4. The method of claim 1 wherein each bin is associated with a corresponding pattern of functional die within the panel.
5. The method of claim 1 , wherein the first die and the second die share a common dimension and wherein the M×N array includes at least three die in at least one of the array dimensions.
6. The method of claim 1 , wherein the M ×N array is selected from a group of arrays consisting of a 2×1 array and a 2×2 array and wherein the first die and the second die are of different dimensions.
7. The method of claim 1 , wherein the first wafer and the second wafer are of different dimensions.
8. The method of claim 1 , wherein the second die is a processor die and the first die is a memory die.
9. A method of assembling of an electronic device, comprising:
dividing a first wafer having a plurality of die into a set of multiple-die panels, wherein a panel includes an M×N array of a first sets of dies, wherein each panel of the set of multiple-die panels includes a plurality of the die from the first wafer;
testing a second wafer comprising a plurality of second sets of dies to identify the location of functional second sets of dies within the second wafer;
determining panel sites of the second wafer, wherein the panel sites include an M×N array of second sets of dies, wherein determining the panel sites of the second wafer comprises selecting panel sites to maximize the number of panel sites having a panel site yield exceeding a specified threshold wherein a panel site yield indicates the number of functional second sets of dies in a panel site;
binning the panel sites of the second wafer into one of multiple bins, wherein each bin is associated with a corresponding pattern of functional second die within the panel site;
bonding a panel to a panel site of a second wafer to form a panel stack; and
sawing the panel stack into a set of electronic devices, each electronic device comprising a first die bonded to a second die.
10. The method of claim 9 , wherein the first die and the second die share a common dimension and wherein the M ×N array includes at least three die in at least one of the array dimensions.
11. The method of claim 9 , wherein the M×N array is selected from a group of arrays consisting of a 2×1 array and a 2×2 array and wherein the first die and the second die are of different dimensions.
12. The method of claim 9 , wherein the first wafer and the second wafer are of different dimensions.
13. The method of claim 9 , wherein the second die is a processor die and the first die is a memory die.
14. A method of assembling an electronic device, comprising:
sawing a first wafer having a plurality of first sets of dies into a panel comprising an M×N array of first die, wherein either M or N is greater than 1, wherein each panel includes a plurality of first sets of dies;
forming a panel site by bonding the panel to a panel site of a second wafer having a plurality of second sets of dies, wherein the panel site encompasses an M×N array of the second sets of dies;
testing the first wafer to identify functional first sets of dies and testing the second wafer to identify functional second sets of dies;
selecting a panel and a corresponding panel site for bonding based upon a matching pattern of functional die in the panel and the panel site; and
sawing the panel site into a device comprising a first sets of dies from the panel bonded to a second sets of dies from the panel site.
15. The method of claim 14 , further comprising testing the first wafer to identify functional first die and discarding a panel if a percentage of functional first die is less than a specified threshold.
16. The method of claim 14 , further comprising testing the second wafer to identify functional second die and eliminating a panel site if a percentage of functional second is less than a specified threshold.