Integrated circuit comprising error correction logic, and a method of error correction
View Patent ↗An integrated circuit comprises forward error correction (FEC) decoder logic being coupled to memory and arranged to receive data, comprising application data, from a host application process. The FEC decoder logic performs error detection upon the received data. Logic is further arranged to transmit error free application data back to the host application process prior to performing error correction; and store in memory only application data in which errors are detected.
1. An integrated circuit comprising:
forward error correction (FEC) decoder logic arranged to receive data, comprising application data, from a host application process; and perform error detection upon the received data;
wherein the FEC decoder logic comprises or is operably coupled to logic arranged to transmit error free and erroneous application data back to the host application process; generate error correction information; and transmit the error correction information to the host application process; wherein the FEC decoder logic is adapted to generate an error correction patch comprising the error correction information.
2. The integrated circuit of claim 1 further comprising:
column building logic adapted to build MPE columns from received MPE data comprising application data; and
error detection logic adapted to detect a presence of one or more errors within the MPE columns, and initiate a transmission of erroneous and error free application data back to the host application process, in response thereto.
3. The integrated circuit of claim 2 further comprising:
error location and value computation logic operably coupled to the error detection logic and adapted to determine a location of value of one or more detected errors; and
patch building logic operably coupled to the error location and value computation logic and adapted to generate error correction patches, and to initiate a transmission of error correction patches to the host application process.
4. The integrated circuit of claim 1 wherein by the FEC decoder logic is adapted to perform cyclic redundancy check (CRC) computation to generate one or more syndromes for detecting a presence of errors.
5. The integrated circuit of claim 4 wherein the FEC decoder logic is adapted to use one or more syndromes within error location and value computations.
6. The integrated circuit of claim 1 wherein the application data comprises Internet Protocol (IP) datagram data.
7. The integrated circuit of claim 6 wherein the FEC decoder logic is adapted to use one or more RS columns within error location and value computations.
8. The integrated circuit of claim 1 wherein the received data comprises multi-protocol encapsulation (MPE) data.
9. The integrated circuit of claim 8 wherein the FEC decoder logic is adapted to build an MPE column with the MPE data, and upon building a complete MPE column, performing error detection upon the complete MPE column.
10. The integrated circuit of claim 9 wherein the FEC decoder logic is adapted to determine whether the MPE column comprises application data or a Reed Solomon (RS) column.
11. The integrated circuit of claim 9 wherein the FEC decoder logic is adapted to determine if an MPE column is the last MPE column of an MPE-FEC frame, and if the column is the last column, the FEC decoder performs error location and value computation for one or more detected errors substantially simultaneously upon a number of erroneous columns within the MPE-FEC frame.
12. A method for performing forward error correction, the method comprising the steps of:
receiving data comprising application data from a host application process;
performing error detection upon the received data;
transmitting error free and erroneous application data back to the host application process;
generating error correction information comprising an error correction patch; and
transmitting error correction information to the host application process.
13. The method of claim 12 further comprising performing cyclic redundancy check (CRC) computations to generate one or more syndromes for detecting a presence of errors.
14. The method of claim 13 further comprising using one or more syndromes within error location and value computations.
15. The method of claim 12 wherein the application data comprises Internet Protocol (IP) datagram data.
16. The method of claim 12 wherein the received data comprises multi-protocol encapsulation (MPE) data.
17. The method of claim 16 further comprises building an MPE column with the MPE data, and upon building a complete MPE column, performing error detection upon the complete MPE column.
18. The method of claim 17 further comprises determining whether the MPE column comprises application data or a Reed Solomon (RS) column.
19. The method of claim 18 further comprises using RS columns within error location and value computations.
20. The method of claim 17 further comprises:
determining if an MPE column is the last MPE column of an MPE-FEC frame, and if the column is the last column;
performing error location and value computation for detected errors substantially simultaneously upon a number of erroneous columns within the MPE-FEC frame.