Electrostatic discharge circuit and method therefor
View Patent ↗An ESD protection circuit ( 81 ) and a method for providing ESD protection is provided. In some embodiments, an N-channel transistor ( 24 ), which can be ESD damaged, is selectively turned on and made conducting. The purpose of turning on the N-channel transistor ( 24 ) is to maximize the Vt1 of the N-channel transistor ( 24 ). Vt1 is the drain-to-source voltage point at which the parasitic bipolar action of the N-channel transistor ( 24 ) first occurs. In some embodiments, the ESD protection circuit ( 81 ) includes a diode ( 64 ) which provides an additional current path from the I/O pad 31 to a first power supply node ( 76 ).
1. An integrated circuit having ESD protection, comprising:
an output pad for communicating external to the integrated circuit;
a resistive element having a first terminal coupled to the output pad and having a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the resistive element, a second current electrode coupled to a first voltage supply node, and a first control electrode, wherein the first transistor comprises an output buffer transistor to be protected during an ESD event, wherein during the ESD event the control electrode of the first transistor is coupled to the first voltage supply node via a biasing circuit, and wherein during the ESD event, said biasing circuit applies a voltage to the first control electrode of the first transistor that is approximately equal to a voltage at a circuit node located between the first current electrode of the first transistor and the second terminal of the resistive element, and wherein said ESD circuit is used to provide ESD protection on an integrated circuit, and wherein said biasing circuit is disabled during normal operation of the integrated circuit;
a first diode having a first terminal coupled to the second terminal of the resistive element and a second terminal coupled to a second voltage supply node;
a second diode having a first terminal coupled to the output pad and a second terminal coupled to the second voltage supply node;
a second transistor having a first current electrode coupled to the second voltage supply node, a second current electrode coupled to the first voltage supply node, and a second control electrode; and
a trigger circuit coupled to the second control electrode.
2. An integrated circuit as in claim 1 , wherein the circuit node is located at the second terminal of the resistive element.
3. An integrated circuit as in claim 1 , wherein the circuit node is located at the first current electrode of the first transistor.
4. An integrated circuit as in claim 1 , wherein the first transistor comprises an NMOS output buffer transistor.
5. An integrated circuit as in claim 1 , wherein the first transistor comprises an NMOS transistor to be protected during the ESD event.
6. An integrated circuit as in claim 1 , wherein the first transistor comprises a PMOS output buffer transistor.
7. An integrated circuit as in claim 1 , wherein the first transistor comprises a PMOS transistor to be protected during the ESD event.
8. An integrated circuit as in claim 1 , wherein the trigger circuit, in response to the ESD event, actively couples a voltage approximately equal to a voltage on the second voltage supply node onto the second control electrode of the second transistor.
9. An integrated circuit as in claim 1 , wherein the second diode is part of a primary current path during an ESD event, and wherein the resistive element and the first diode are part of a secondary current path during the ESD event.
10. An integrated circuit as in claim 9 , wherein during the ESD event, current flowing through the resistive element, as part of the secondary current path, reduces a voltage at the first current electrode of the first transistor below a voltage at the output terminal.
11. A method for providing ESD protection for an NMOS transistor having a first current electrode coupled via a resistive element to an output terminal, a second current electrode coupled to a first voltage supply node, and a control electrode, wherein said NMOS transistor is located on an integrated circuit, comprising:
providing current via a primary current path during an ESD event from the output terminal to the first voltage supply node via a first diode, a second voltage supply node, and a rail clamp coupled between the first and second voltage supplies; and
providing current via a secondary current path during the ESD event from the output terminal to the first supply voltage via the resistive element, a second diode, the second voltage supply node, and the rail clamp,
wherein the rail clamp is actively driven by a trigger circuit;
during the ESD event, using a biasing circuit, applying a voltage to the control electrode of the NMOS transistor, that is approximately equal to a voltage at a circuit node located between the first current electrode of the NMOS transistor and the resistive element; and
disabling the biasing circuit during normal operation of the integrated circuit.
12. A method as in claim 11 , wherein during the ESD event, the current via the secondary current path reduces a voltage at the first current electrode of the NMOS transistor.
13. A method for providing ESD protection for a PMOS transistor having a first current electrode coupled via a resistive element to an output terminal, a second current electrode coupled to a first voltage supply node, and a control electrode, wherein said PMOS transistor is located on an integrated circuit, comprising:
providing current via a primary current path during an ESD event from the output terminal to the first voltage supply node via a first diode, a second voltage supply node, and a rail clamp coupled between the first and second voltage supplies; and
providing current via a secondary current path during the ESD event from the output terminal to the first supply voltage via the resistive element, a second diode, the second voltage supply node, and the rail clamp,
wherein the rail clamp is actively driven by a trigger circuit;
during the ESD event, using a biasing circuit, applying a voltage to the control electrode of the PMOS transistor, that is approximately equal to a voltage at a circuit node located between the first current electrode of the PMOS transistor and the resistive element; and
disabling the biasing circuit during normal operation of the integrated circuit.
14. A method as in claim 13 , wherein during the ESD event, the current via the secondary current path reduces a voltage at the first current electrode of the PMOS transistor.
15. An ESD circuit comprising:
an output terminal;
a resistive element having a first terminal coupled to the output terminal and a second terminal;
an output buffer transistor having a first current electrode coupled to the second terminal of the resistive element, a second current electrode coupled to a first voltage supply node, and a control electrode;
a rail clamp coupled to the first voltage supply node and a second voltage supply node, the rail clamp comprising:
a trigger circuit for detecting an ESD event, the trigger circuit having a trigger output; and
a device having a control electrode coupled to the trigger output;
means for providing a primary current path during the ESD event from the output terminal to the first voltage supply node via a first diode, the second voltage supply node, and the rail clamp;
means for providing a secondary current path during the ESD event from the output terminal to the first voltage supply node via the resistive element, a second diode, the second voltage supply node, and the rail clamp; and
means for applying a voltage to the control electrode of the output buffer transistor, that is approximately equal to a voltage at a circuit node located between the first current electrode of the output buffer transistor and the second terminal of the resistive element, wherein said ESD circuit is used to provide ESD protection on an integrated circuit, and wherein the means for applying the voltage is disabled during normal operation of the integrated circuit.
16. An ESD circuit as in claim 15 , wherein the output buffer transistor comprises an NMOS transistor.
17. An ESD circuit as in claim 15 , wherein the output buffer transistor comprises a PMOS transistor.