System, method and program product for well-bias set point adjustment
View Patent ↗A well-bias system dynamically adjusts well-bias set points to optimal levels across an integrated circuit (IC) for enhanced power savings and component reliability during a standby or low-power mode of operation. A controller within the IC determines if the chip power supply voltage will be reduced during an imminent standby or low power mode and sets a register controlling a negative well-bias set point for asserting well-bias to charge wells of the IC accordingly. To minimize leakage current without compromising reliability, the well-bias set point is set to (1) an optimal well-bias set point if a reduced supply voltage is to be applied to the IC, or (2) a minimum well-bias set point when a nominal or high supply voltage is to be applied to the IC.
1. A system comprising:
a well-bias circuit receiving a well-bias set point at an input, and providing bias corresponding to the well-bias set point to a charge well coupled to an output; and
logic coupled to the input of the well-bias circuit for setting the well-bias set point to a first value when the system enters into a first mode of operation and setting the well-bias set point to a second value when the system enters into a second mode of operation, wherein the first mode of operation is a low power mode where the system operates at a supply voltage of a magnitude lower than a supply voltage provided to the system during the second mode of operation.
2. The system of claim 1 , further comprising:
an enable circuit having an input coupled to the logic for receiving an enable signal and an output coupled to the well-bias circuit that enables the output of the well-bias circuit in response to receiving the enable signal, wherein the logic sends the enable signal in response to the system entering into either the first or second mode of operation.
3. The system of claim 1 , wherein the logic comprises a data processing component.
4. The system of claim 1 , wherein the first value is a optimized well-bias at the lower supply voltage.
5. The system of claim 1 , wherein the second value is a minimum well-bias of the well-bias circuit.
6. The system of claim 5 , wherein the supply voltage provided to the system during the second mode of operation is a nominal bias condition.
7. A system comprising:
a well-bias circuit receiving a well-bias set point at an input, and providing bias corresponding to the well-bias set point to a charge well coupled to an output;
logic coupled to the input of the well-bias circuit for setting the well-bias set point to a first value when the system enters into a first mode of operation and setting the well-bias set point to a second value when the system enters into a second mode of operation; and
one or more registers coupled to the logic and the well-bias circuit, wherein the logic sets the one or more registers to the well-bias set point, and further wherein the well-bias circuit retrieves the well-bias set point from the registers.
8. A system comprising:
a well-bias circuit receiving a well-bias set point at an input, and providing bias corresponding to the well-bias set point to a charge well coupled to an output;
logic coupled to the input of the well-bias circuit for setting the well-bias set point to a first value when the system enters into a first mode of operation and setting the well-bias set point to a second value when the system enters into a second mode of operation; and
one or more storage elements coupled to the logic, wherein the storage elements store the first values, and wherein the first values are retrieved from the storage elements by the logic for setting the well-bias points during the first mode of operation.
9. A method comprising:
determining that an integrated circuit is to enter into a mode of operation;
determining if a lower supply voltage relative to a nominal supply voltage of the integrated circuit will be applied during the mode of operation;
setting a well-bias circuit to apply a first level of well-bias to the charge wells of the integrated circuit if the lower supply voltage will be supplied during the mode of operation; and
setting the well-bias circuit to apply a second level of well-bias to the charge wells of the integrated circuit if the lower supply voltage will not be supplied to the integrated circuit during the mode of operation.
10. The method of claim 9 , wherein the first level of well-bias is an optimal well-bias for the integrated circuit when the lower supply voltage is supplied to the integrated circuit.
11. The method of claim 9 , wherein the second level is a minimum level of well-bias for the well-bias circuit.
12. The method of claim 9 , further comprising:
reading the first level from memory cells in the integrated circuit.
13. The method of claim 9 , further comprising in registers, wherein setting the well-bias circuit includes transferring the first level from registers of the integrated circuit storing the first level to the well-bias circuit and setting the well-bias in accordance with the transferred first level.
14. The method of claim 9 , further comprising testing the integrated circuit, wherein testing comprises:
setting a register to each possible register value;
setting the well-bias on the charge wells in response to each possible register value set in the register; and
measuring the leakage current for each setting of the well-bias in response to each possible register value set in the register.
15. The method of claim 14 , wherein the first level is the register value producing the lowest measured leakage current in the integrated circuit.
16. The method of claim 9 , wherein the mode of operation is a low power mode where the system operates at a supply voltage of a magnitude lower than a nominal supply voltage.
17. An article of manufacture comprising a machine-readable medium including program logic embedded therein for setting a well-bias point that causes circuitry to perform the steps of:
determining that an integrated circuit is to enter into a low power mode of operation where the system operates at a supply voltage of a magnitude lower than a nominal supply voltage;
determining if a lower supply voltage relative to a nominal supply voltage of the integrated circuit will be applied during the low power mode of operation;
setting a well-bias circuit to apply a first level of well-bias to the charge wells of the integrated circuit if the lower supply voltage will be supplied during the low power mode of operation; and
setting the well-bias circuit to apply a second level of well-bias to the charge wells of the integrated circuit if the lower supply voltage will not be supplied to the integrated circuit during the low power mode of operation.
18. The article of manufacture of claim 17 , wherein the first level of well-bias is an optimal well-bias for the integrated circuit when the lower supply voltage is supplied to the integrated circuit.
19. The article of manufacture of claim 17 , wherein the second level is a minimum level of well-bias for the well-bias circuit.