Load independent voltage regulator
An integrated circuit package ( 202 ) includes a voltage regulator ( 208 ) and a power-out pin ( 236 ) for coupling to a load circuit ( 210 ) via a connection ( 234 ) external to the integrated circuit package and for coupling to an output ( 230 ) of the voltage regulator via a connection ( 224, 228, 226 and 231 ) internal to the integrated circuit package. The internal connection has a series resistance that causes a voltage drop due to a load current. The voltage regulator compensates for the voltage drop in the internal connection using a current feedback circuit, in which the current fed back is proportional to the voltage drop caused by the series resistance of the internal connection.
1. An integrated circuit package, comprising:
an integrated circuit, the integrated circuit including a voltage regulator, the voltage regulator having an output for providing a regulated voltage;
a power-out pin having an external portion for coupling to a load circuit via a connection external to the integrated circuit package and having an internal portion for coupling to the output of the voltage regulator; and
means for coupling the power-out pin to the output of the voltage regulator, the means for coupling having a series resistance;
wherein the voltage regulator includes means for compensating for a voltage drop caused by the means for coupling, the means for compensating comprising a current feedback circuit wherein a current that is fed back is proportional to the voltage drop caused by the means for coupling.
2. The integrated circuit package of claim 1 , in which the integrated circuit is fabricated using a complementary metal oxide semiconductor (CMOS) process.
3. The integrated circuit package of claim 1 , in which the integrated circuit is fabricated using bipolar transistors.
4. The integrated circuit package of claim 1 , in which the means for coupling includes a metal run on the integrated circuit between the output of the voltage regulator and a bond pad on the integrated circuit, and a wire bond between the bond pad and the internal portion of the power-out pin.
5. The integrated circuit package of claim 1 in which the voltage regulator includes
a power transistor having a gate, a drain coupled to an output of the voltage regulator, and a source coupled to a power supply for supplying an input current to the voltage regulator,
a differential amplifier having an output coupled to the gate of the power transistor and an input coupled to a voltage reference,
a second transistor having a current that mirrors a predetermined fraction of the input current, and
a resistor network coupled to the output of the voltage regulator and to ground, the resistor network having a tap, the tap coupled to another input of the differential amplifier and to a drain of the second transistor.
6. A voltage regulator, comprising:
a power transistor having a gate, a drain coupled to an output of the voltage regulator, and a source coupled to a power supply for supplying an input current to the voltage regulator;
a differential amplifier having an output coupled to the gate of the power transistor and an input coupled to a voltage reference;
means for coupling the output of the voltage regulator to a load circuit, the means for coupling having a series resistance;
a second transistor having a current that mirrors a predetermined fraction of the input current; and
a resistor network coupled to the output of the voltage regulator and to ground, the resistor network having a tap, the tap coupled to another input of the differential amplifier and to a drain of the second transistor,
wherein a feedback current from the tap of the resistor network to the drain of the second transistor is proportional to a voltage drop across the means for coupling, and wherein a voltage at the tap of the resistor network remains unchanged in spite of changes in the feedback current.
7. The voltage regulator of claim 6 , including a third transistor connected in a current mirror configuration with the power transistor, the third transistor having a drain coupled to a gate of the second transistor, wherein the predetermined fraction is set by a first ratio between a gate area of the third transistor to a gate area of the power transistor.
8. The voltage regulator of claim 6 , including a fourth transistor connected in a current mirror configuration with the second transistor, wherein the predetermined fraction is set by a second ratio between a gate area of the fourth transistor to a gate area of the second transistor.
9. The voltage regulator of claim 6 , including
a third transistor connected in a current mirror configuration with the power transistor, the third transistor having a drain coupled to a gate of the second transistor, and
a fourth transistor connected in a current mirror configuration with the second transistor,
wherein the predetermined fraction is set by a combination of a first ratio between a gate area of the third transistor to a gate area of the power transistor, and a second ratio between a gate area of the fourth transistor to a gate area of the second transistor.
10. The voltage regulator of claim 6 , implemented in an integrated circuit fabricated using a multiple-oxide complementary metal oxide semiconductor (CMOS) process.
11. The voltage regulator of claim 10 in which the load circuit is located external to the integrated circuit.
12. The voltage regulator of claim 10 in which the load circuit is in the integrated circuit.
13. The voltage regulator of claim 10 , in which the integrated circuit comprises at least one thin oxide area and at least one thick oxide area.
14. The voltage regulator of claim 13 in which the voltage regulator is located in a thick oxide area.
15. The voltage regulator of claim 13 in which the load circuit is located in a thin oxide area.
16. An integrated circuit package, comprising:
an integrated circuit;
a voltage regulator having a regulated voltage signal output;
a resistance within the integrated circuit package, the resistance having an input and an output, the regulated voltage signal output being at a same electrical node as the input of the resistance; and
a load circuit having an input and an output, the output of the load circuit being electrically coupled to ground and the input of the load circuit being electrically coupled to the output of the resistance, wherein the voltage regulator includes a resistor ladder network coupled to ground and to the same electrical node as the input of the resistance, the resistor ladder network comprising a first resistor and a second resistor and producing a feedback voltage determined by a ratio of a resistance of the first resistor to a resistance of the second resistor, the feedback voltage being proportional to the voltage at the input of the resistance, and wherein the voltage regulator includes means for compensating for a voltage drop caused by the resistance, the means for compensating comprising a current feedback circuit wherein a current that is fed back is proportional to the voltage drop caused by the resistance.
17. The integrated circuit package of claim 16 , in which the load circuit is external to the integrated circuit package.
18. The integrated circuit package of claim 16 , in which the load circuit is within the integrated circuit package.
19. The integrated circuit package of claim 16 , in which the integrated circuit is fabricated using a complementary metal oxide semiconductor (CMOS) process.
20. The integrated circuit package of claim 16 , in which the integrated circuit uses bipolar transistors.