Delay circuitry and method therefor
View Patent ↗One use for delay adjustment circuit ( 32 ), coarse-grain delay offset circuit ( 34 ), and fine-grain delay synthesis circuit ( 36 ) may be as part of a delay replication circuit ( 30 ) used to replicate the frequency versus voltage behavior of an integrated circuit ( 29 ). Also, a circuit ( 30 ) and method for determining optimal power and frequency metrics of integrated circuit ( 29 ) is also described. In addition, a method for determining programmable coefficients to replicate frequency and supply voltage correlation is described.
1. A delay circuit comprising:
a first delay portion for receiving an input signal and delaying the input signal by a first predetermined amount, the first delay portion comprising a first plurality of same-type logic gates within the first plurality comprising transistors for delaying the input signal, the transistors of the first plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length; and
a second delay portion coupled in series with the first delay portion for delaying the input signal by a second predetermined amount in addition to the first predetermined amount, the second delay portion comprising a second plurality of same-type logic gates within the second plurality comprising transistors for delaying the input signal, the transistors of the second plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length, at least one of transistor threshold voltage, transistor gate length and type of logic gate differing between the first delay portion and the second delay portion.
2. The delay circuit of claim 1 further comprising:
a third delay portion coupled in series with the second delay portion for delaying the input signal by a third predetermined amount in addition to the first predetermined amount and the second predetermined amount, the third delay portion comprising a third plurality of same-type logic gates within the third plurality comprising transistors for delaying the input signal, the transistors of the third plurality of same-type logic gates having a substantially same transistor threshold voltage and a substantially same transistor gate length, at least one of transistor threshold voltage, transistor gate length and type of logic gate differing from each of the first delay portion and the second delay portion.
3. The delay circuit of claim 2 wherein transistor gate length dimensions of the transistors of the first plurality of same-type logic gates differ from transistor gate length dimensions of the transistors of the second plurality of same-type logic gates and transistor gate length dimensions of the transistors of the third plurality of same-type logic gates.
4. The delay circuit of claim 2 wherein the first plurality of same-type logic gates differs in logic gate function from at least one of the second plurality of same-type logic gates and the third plurality of same-type logic gates.
5. The delay circuit of claim 1 further comprising a multiplexer in each of the first delay portion and the second delay portion for selecting an amount of delay provided by each of the first delay portion and the second delay portion.
6. The delay circuit of claim 1 wherein each of the first delay portion and the second delay portion comprise a plurality of selectable taps for selecting one of a plurality of delay amounts for the first predetermined amount and the second predetermined amount in response to one or more control signals.
7. The delay circuit of claim 1 wherein the transistor threshold voltage of transistors in the first delay portion differs from the transistor threshold voltage of transistors in the second delay portion.
8. A method of delaying an input signal comprising:
receiving an input signal and delaying the input signal by a first predetermined amount by using a first plurality of same-type logic gates comprising transistors;
forming the transistors of the first plurality of logic gates to each have a substantially same first threshold voltage and a substantially same first transistor gate length;
coupling a second delay portion in series with the first delay portion for delaying the input signal by an additional second predetermined amount, the second delay portion comprising a second plurality of same-type logic gates comprising transistors; and
forming the transistors of the second plurality of same-type logic gates to each have a substantially same second threshold voltage and a substantially same second transistor gate length, at least one of logic gate type, transistor threshold voltage and transistor gate length differing between the transistors of the first plurality and the transistors of the second plurality.
9. The method of claim 8 further comprising:
coupling a third delay portion in series with the second delay portion, the third delay portion comprising a third plurality of same-type logic gates comprising transistors, the transistors of the third plurality of logic gates each having a substantially same third threshold voltage and a substantially same third transistor gate length, at least one of the third threshold voltage, the third transistor gate length or logic gate type of the third delay portion differing from transistors of first delay portion or the second delay portion; and
delaying the input signal by a third predetermined amount in addition to the first predetermined amount and the second predetermined amount.
10. The method of claim 8 further comprising:
sizing transistor gate length dimensions of the transistors of the first plurality of same-type logic gates to be different from transistor gate length dimensions of the transistors of the second plurality of same-type logic gates and transistor gate length dimensions of the transistors of the third plurality of same-type logic gates.
11. The method of claim 8 further comprising:
sizing transistor gate length dimensions of the transistors of the first plurality of same-type logic gates to be different from transistor gate length dimensions of the transistors of the second plurality of same-type logic gates.
12. The method of claim 8 further comprising:
multiplexing delay units within each of the first delay portion and the second delay portion for selecting an amount of variable delay provided by each of the first delay portion and the second delay portion.
13. The method of claim 8 further comprising:
forming a plurality of selectable taps in each of the first delay portion and the second delay portion for selecting one of a plurality of delay amounts for the first predetermined amount and the second predetermined amount in response to one or more control signals.
14. The method of claim 8 further comprising:
implementing a different logic function for the first plurality of same-type logic gates as compared to the second plurality of same-type logic gates to delay the input signal.
15. A method of delaying an input signal comprising:
receiving the input signal;
delaying the input signal by a first predetermined amount by using a first plurality of transistors forming logic gates used as delay elements and having a same logic function, each of the first plurality of transistors having a substantially equal first threshold voltage and first gate length; and
subsequently delaying the input signal by a second predetermined amount by using a second plurality of transistors, each of the second plurality of transistors forming logic gates used as delay elements and having a same second logic function, each of the second plurality of transistors having a substantially equal second threshold voltage and second gate length, wherein at least one of the first logic function, the first threshold voltage and the first gate length correspondingly differs from at least one of the second logic function, the second threshold voltage and the second gate length.
16. The method of claim 15 further comprising:
subsequently delaying the input signal by a third predetermined amount in addition to the first predetermined amount and the second predetermined amount by using a third plurality of transistors that form logic gates used as delay elements and having a third logic function, each of the third plurality of transistors having a substantially equal third threshold voltage and third gate length, wherein at least one of the third logic function, the third threshold voltage and the third gate length corresponding differs from the first and second logic functions, the first and second threshold voltages and the first and second gate lengths.
17. The method of claim 15 wherein the first threshold voltage differs from the second threshold voltage.
18. The method of claim 15 wherein the first gate length differs from the second gate length.
19. The method of claim 15 wherein the first logic function of the first plurality of transistors differs from the second logic function of the second plurality of transistors.
20. The method of claim 15 further comprising:
forming a plurality of selectable taps within each of the first plurality of transistors and the second plurality of transistors for selecting one of a plurality of delay amounts for the first predetermined amount and the second predetermined amount in response to one or more control signals.