IP Library Granted Patent US 7,444,012
Granted Patent B2
US 7,444,012 · App. 10/626,781 · Granted Oct 28, 2008

Method and apparatus for performing failure analysis with fluorescence inks

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Quick Facts
Patent No.
US 7,444,012
App. No.
10/626,781
Granted
Oct 28, 2008
Kind
B2
Abstract

A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation material containing the dye. The prepared device sample is then sectioned to facilitate viewing a cross section face of the device under inspection. Lastly, a dark field analysis on the prepared device sample is performed with the use of dark field illumination. Responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained.

Claims (35)

1. A method for performing failure analysis on a semiconductor device under inspection, comprising:

preparing of a sample of the semiconductor device under inspection using an encapsulation material containing a dye, the prepared device sample possibly including at least one failure area containing wicked in encapsulation material containing the dye;

sectioning the prepared device sample to facilitate viewing a cross section face of the device under inspection;

performing a dark field analysis on the prepared device sample with the use of dark field illumination, wherein responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained; and

repeating the sectioning of the prepared device sample to facilitate viewing another cross-section face of the device under inspection, and performing dark field analysis on the another cross section face of the prepared device sample with the use of dark field illumination.

2. The method of claim 1 , wherein the semiconductor device includes a wafer level chip scale packaged semiconductor device.

3. The method of claim 1 , wherein the dye includes at least one fluorescent dye selected from the group consisting of a Xanthane, Naphthalimide, Perylene, Courmarin, and Fluorescein based family.

4. The method of claim 1 , wherein the dye includes a dye pigment that is added to an uncured epoxy encapsulation material.

5. The method of claim 4 , wherein preparing the device sample further includes placing the sample into a container along with the uncured epoxy containing the dye pigment, placing the same in a vacuum chamber, and maintaining the same under vacuum within the vacuum chamber for a duration of time sufficient for allowing the uncured epoxy encapsulation material containing dye to wick into a failure area of delamination extending from an exterior to an interior of the device sample.

6. The method of claim 5 , further including configuring the conditions within the vacuum chamber to promote wicking of the encapsulation material containing dye into the failure area.

7. The method of claim 5 , wherein preparing the device sample further includes employing a vacuum purge cycle subsequent to placing the device sample under vacuum within the vacuum chamber for the duration of wicking, allowing the dye and encapsulation material to return to standard ambient conditions, and then curing the encapsulation material containing the dye.

8. The method of claim 4 , further wherein the encapsulation material includes a two component encapsulant comprised of a resin and a hardener.

9. The method of claim 1 , wherein sectioning of the sample includes rough grinding, followed by fine grinding, and then polishing, prior to subjecting the sample to the dark field analysis.

10. The method of claim 1 , wherein performing the dark field analysis includes capturing an image of the cross section of the prepared device sample under dark field illumination.

11. The method of claim 1 , further wherein performing the dark field analysis includes using a compound microscope configured for dark field illumination and inspection and wherein the compound microscope includes an image capture system coupled to the compound microscope for capturing an image of the cross section face of the device under inspection.

12. The method of claim 11 , wherein the captured image include a digital image.

13. The method of claim 1 , wherein the dark field illumination includes use of a full complement of light for illuminating the cross section face of the device under inspection.

14. A method for performing failure analysis on a semiconductor device under inspection, comprising:

preparing of a sample of the semiconductor device under inspection using an encapsulation material containing a dye, the prepared device sample possibly including at least one failure area containing wicked in encapsulation material containing the dye;

sectioning the prepared device sample to facilitate viewing a cross section face of the device under inspection;

performing a dark field analysis on the prepared device sample with the use of dark field illumination, wherein responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained; and

prior to preparing and sectioning the device sample, performing an initial assessment of the device under inspection with the use of acoustic scanning to determine a location for cross sectioning the device sample, the location corresponding to a potential failure area or point of delamination in the device sample.

15. A method of manufacturing a semiconductor device comprising:

fabricating the semiconductor device;

performing a failure analysis on the semiconductor device, the failure analysis including

(a) preparing of a sample of the semiconductor device under inspection using an encapsulation material containing a dye, the prepared device sample possibly including at least one failure area containing wicked in encapsulation material containing the dye, (b) sectioning the prepared device sample to facilitate viewing a cross section face of the device under inspection, and (c) performing a dark field analysis on the prepared device sample with the use of dark field illumination, wherein responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained;

adjusting the manufacturing process in response to an outcome of the failure analysis; and

repeating the sectioning of the prepared device sample to facilitate viewing another cross-section face of the device under inspection, and performing dark field analysis on the another cross section face of the prepared device sample with the use of dark field illumination.

16. The method of claim 15 , wherein the semiconductor device includes a wafer level chip scale packaged semiconductor device.

17. The method of claim 15 , wherein the dye includes at least one fluorescent dye selected from the group consisting of a Xanthane, Naphthalimide, Perylene, Courmarin, and Fluorescein based family.

18. The method of claim 15 , wherein the dye includes a dye pigment that is added to an uncured epoxy encapsulation material.

19. The method of claim 18 , wherein preparing the device sample further includes placing the sample into a container along with the uncured epoxy containing the dye pigment, placing the same in a vacuum chamber, and maintaining the same under vacuum within the vacuum chamber for a duration of time sufficient for allowing the uncured epoxy encapsulation material containing dye to wick into a failure area of delamination extending from an exterior to an interior of the device sample.

20. The method of claim 15 , further wherein performing the dark field analysis includes using a compound microscope configured for dark field illumination and inspection and wherein the compound microscope includes an image capture system coupled to the compound microscope for capturing an image of the cross section face of the device under inspection.

21. The method of claim 15 , further comprising:

prior to preparing and sectioning the device sample, performing an initial assessment of the device under inspection with the use of acoustic scanning to determine a location for cross sectioning the device sample, the location corresponding to a potential failure area or point of delamination in the device sample.

Assignments (24)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0807 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 12, 2009
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 022380/0409 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 24, 2003
From: WHITE, JERRY L; LEE, RUSSELL T.
To: MOTOROLA, INC.
Reel/Frame 014328/0564 →