Electronic device including semiconductor fins and a process for forming the electronic device
View Patent ↗An electronic device can include a first semiconductor fin and a second semiconductor fin, each spaced-apart from the other. The electronic device can also include a bridge lying between and contacting each of the first semiconductor fin and the second semiconductor fin along only a portion of length of each of the first semiconductor fin and the second semiconductor fin, respectively. In another aspect, a process for forming an electronic device can include forming a first semiconductor fin and a second semiconductor fin from a semiconductor layer, each of the first semiconductor fin and the second semiconductor fin spaced-apart from the other. The process can also include forming a bridge that contacts the first semiconductor fin and second semiconductor fin. The process can further include forming a conductive member, including a gate electrode, lying between the first semiconductor fin and second semiconductor fin.
1. A process of forming an electronic device comprising:
providing a base layer including a semiconductor material, an insulating layer overlying the base layer, and a semiconductor layer overlying the insulating layer;
forming a first semiconductor fin from the semiconductor layer, wherein forming the first semiconductor fin comprises forming the first semiconductor fin spaced apart from the base layer and having a first length;
forming a second semiconductor fin from the semiconductor layer and spaced-apart from the first semiconductor fin, wherein forming the second semiconductor fin comprises forming the second semiconductor fin spaced apart from the base layer and having a second length;
forming a first bridge lying between the first semiconductor fin and the second semiconductor fin, wherein forming the first bridge comprises forming the first bridge such that the first bridge contacts the first semiconductor fin along only a portion of the first length, and the second semiconductor fin along only a portion of the second length;
forming a first source/drain region within the first semiconductor fin and a second source/drain region within the second semiconductor fin, wherein the first and second source/drain regions are spaced-apart from and electrically coupled to each other; and
forming a third source/drain region within the first semiconductor fin and a fourth source/drain region within the second semiconductor fin, wherein the third and fourth source/drain regions are spaced-apart from and electrically coupled to each other.
2. The process of claim 1 , further comprising forming a conductive member overlying the first bridge and including a gate electrode, wherein the conductive member overlies and is spaced-apart from the first semiconductor fin and the second semiconductor fin.
3. The process of claim 2 , wherein forming a first insulating layer lying between the conductive member and the first semiconductor fin and between the conductive member and the second semiconductor fin.
4. The process of claim 1 , wherein forming the first semiconductor fin and forming the second semiconductor fin are performed such that lengths of the first and second semiconductor fins are substantially perpendicular to a length of the conductive member, and the first and second semiconductor fins are substantially parallel and lie along different lines as compared to each other.
5. The process of claim 4 , further comprising forming a third semiconductor fin, wherein forming the third semiconductor fin comprises forming the third semiconductor fin having a third length and spaced-apart from each of the first semiconductor fin, the second semiconductor fin, and the first bridge.
6. The process of claim 1 , wherein:
forming the first bridge is performed such that the first bridge contacts the first semiconductor fin between the first source/drain region and the second source/drain region; and
forming the first bridge is performed such that the first bridge contacts the second semiconductor fin between the third source/drain region and the fourth source/drain region.
7. The process of claim 6 , wherein:
forming the first bridge is performed such that the first bridge contacts the first semiconductor fin a first distance from the first source/drain region;
forming the first bridge is performed such that the first bridge contacts the second semiconductor fin a second distance from the third source/drain region; and
the first distance is shorter than the second distance.
8. The process of claim 1 , wherein the electronic device comprises a transistor structure, wherein the process comprises:
patterning the semiconductor layer to form the first semiconductor fin, the second semiconductor fin, and the first bridge;
forming a gate electrode adjacent to opposing sides of the first semiconductor fin and opposing sides of the second semiconductor fin;
forming the first source/drain region and forming a second source/drain region from portions of the first semiconductor fin that are not covered by the gate electrode to define a first channel region lying within the first semiconductor fin, underlying the gate electrode, and between the first source/drain region and the second source/drain region; and
forming the third source/drain region and the fourth source/drain region from portions of the second semiconductor fin that are not covered by the gate electrode to define a second channel region lying with the second semiconductor fin, underlying the gate electrode, and between the third source/drain region and the fourth source/drain region,
wherein the first channel region and the second channel region are configured, such that when the transistor would be on, charge carriers would flow through the first channel region, the second channel region, or any combination thereof in a direction substantially parallel to a primary surface of a base layer.
9. The process of claim 1 , wherein:
forming the first semiconductor fin comprises forming the first semiconductor fin having a first thickness;
forming the second semiconductor comprises forming the second semiconductor fin having a second thickness substantially a same as the first thickness; and
forming the first bridge comprises forming the first bridge having a third thickness less than the first thickness.
10. The process of claim 1 , further including:
providing a substrate including a base layer, a second insulating layer, and the semiconductor layer, wherein the insulating layer lies between the base layer and the semiconductor layer,
wherein the first length of the first semiconductor fin is substantially a same as the second length of the second semiconductor fin.
11. The process of claim 1 , further comprising forming a second bridge lying between the first semiconductor fin and the second semiconductor fin, wherein the second bridge is spaced-apart from the first bridge.
12. The process of claim 1 , further comprising forming a second bridge lying between the first semiconductor fin and the second semiconductor fin wherein:
the first bridge has a third length;
the second bridge has a fourth length;
the first bridge contacts the second bridge along only a portion of the fourth length; and
the second bridge contacts the first bridge along only a portion of the third length.
13. The process of claim 1 , wherein forming the first bridge comprises forming the first bridge from the semiconductor layer.
14. A process of forming an electronic device comprising a transistor, wherein the process includes:
forming a first semiconductor fin;
forming a second semiconductor fin spaced-apart from the first semiconductor fin;
forming a first portion of a semiconductor layer between the first semiconductor fin and the second semiconductor fin and contacting the first semiconductor fin and the second semiconductor fin at locations adjacent to ends of the first and second semiconductor fins;
forming a second portion of the semiconductor layer between the first semiconductor fin and the second semiconductor fin and contacting the first semiconductor fin and the second semiconductor fin at locations adjacent to opposite ends of the first and second semiconductor fins;
forming a conductive member overlying the first semiconductor fin and the second semiconductor fin, wherein forming the conductive member is performed such that a portion of the conductive member lies adjacent to both sides of the first semiconductor fin and lies adjacent to opposite sides of the second semiconductor fin;
forming first source/drain regions that include portions of the first semiconductor fin and the second semiconductor fin and are electrically connected to each other by the first portion of the semiconductor layer; and
forming second source/drain regions that include other portions of the first semiconductor fin and the second semiconductor fin and are electrically connected to each other by the second portion of the semiconductor layer, wherein the second source/drain regions are spaced apart from the first source drain regions,
wherein:
a first channel region of the transistor lies within the first semiconductor fin at a location between the first and second source/drain regions;
a second channel region of the transistor lies within the second semiconductor fin at another location between the first and second source/drain regions; and
when the transistor would be on, charge carriers would flow through first channel region, the second channel region, or any combination thereof in a direction substantially parallel to a primary surface of the electronic device.