Method of forming a semiconductor device
View Patent ↗A method for integrating first and second type devices on a semiconductor substrate includes forming openings within an active semiconductor layer of a dual semiconductor-on-insulator in first and second regions of the semiconductor substrate. First and second non-MOS transistor device implant regions are formed within portions of an intermediate semiconductor layer underlying first and second openings, respectively, in a first device portion, filled with a fill material and planarized. A top surface portion of the active semiconductor layer disposed in-between the first and second openings is exposed, first and second low dose non-MOS transistor device well regions are formed in respective first and second portions of the intermediate semiconductor layer underlying a region in-between the first and second openings. The method further includes forming a salicide blocking layer, forming first and second contact vias within the fill material of the first and second openings, respectively, exposing a portion of the underlying intermediate semiconductor layer, forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer, and saliciding the semiconductor substrate, the salicide blocking layer preventing salicidation of the first and second low dose non-MOS transistor device well regions.
1. A method for integrating a non-MOS transistor device and a CMOS electronic device on a semiconductor substrate, comprising:
providing a semiconductor substrate having an active semiconductor layer, wherein the active semiconductor layer comprises a top semiconductor layer of a dual semiconductor-on-insulator substrate, the top semiconductor layer overlying an insulator, and the insulator overlying an intermediate semiconductor layer;
forming openings within the active semiconductor layer in a first region of the semiconductor substrate and openings within the active semiconductor layer in a second region of the semiconductor substrate, wherein the first region corresponds to a non-MOS transistor device portion of the semiconductor substrate and the second region corresponds to a CMOS electronic device portion of the semiconductor substrate;
forming first and second non-MOS transistor device implant regions within portions of the intermediate semiconductor layer underlying first and second openings, respectively, in the non-MOS transistor device portion;
forming a non-MOS transistor device liner on sidewalls of the openings within the active semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate;
forming a trench liner on sidewalls within the openings of the active semiconductor layer in the CMOS electronic device portion of the semiconductor substrate;
filling the openings of the active semiconductor layer in the non-MOS transistor device portion of the semiconductor substrate and the openings of the active semiconductor layer in the CMOS electronic device portion of the semiconductor substrate with a fill material and planarizing the fill material;
exposing a top surface portion of the active semiconductor layer disposed in-between the first and second openings in the non-MOS transistor device portion of the semiconductor substrate;
forming first and second low dose non-MOS transistor device well regions in respective first and second portions of the intermediate semiconductor layer underlying a region of the active semiconductor layer in-between the first and second openings in the non-MOS transistor device portion of the semiconductor substrate;
forming at least a portion of a CMOS electronic device on the active semiconductor layer within the CMOS electronic device portion of the semiconductor substrate;
forming a salicide blocking layer overlying a region of at least the active semiconductor layer in-between the first and second openings;
forming first and second contact vias within the fill material of the first and second openings, respectively, each contact via extending through the fill material and into the insulator, exposing a portion of the underlying intermediate semiconductor layer;
forming first and second non-MOS transistor device contact regions in exposed portions of the intermediate semiconductor layer of the first and second openings in the non-MOS transistor device portion of the semiconductor substrate;
saliciding the CMOS electronic device portion and a portion of the non-MOS transistor device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the first and second low dose non-MOS transistor device well regions in the non-MOS transistor device portion of the semiconductor substrate; and
forming an interlevel dielectric layer overlying the non-MOS transistor device portion and the CMOS electronic device portion of the semiconductor substrate.
2. The method of claim 1 , wherein forming openings within the active semiconductor layer in the first region and within the active semiconductor layer in the second region comprises one of: (i) simultaneously forming openings in the non-MOS transistor device portion and the CMOS electronic device portion, or (ii) independently forming openings in the non-MOS transistor device portion from openings in the CMOS electronic device portion.
3. The method of claim 1 , further comprising forming contacts within the interlevel dielectric layer to the first and second salicided contact regions, respectively.
4. The method of claim 1 , wherein forming the non-MOS transistor device liners and forming the trench liners comprises one of: (i) simultaneously forming the non-MOS transistor device liners and the trench liners, or (ii) independently forming the non-MOS transistor device liners in the non-MOS transistor device portion from the trench liners in the CMOS electronic device portion.
5. The method of claim 1 , wherein forming the first non-MOS transistor device implant region includes implantation of an implant species having a first conductivity type, and wherein forming the second non-MOS transistor device implant region includes implantation of an implant species having a second conductivity type.
6. The method of claim 1 , wherein forming the first non-MOS transistor device implant region includes forming a photoresist overlying the non-MOS transistor device portion and the CMOS electronic device portion, forming an opening within the photoresist over at least a portion of the first opening, and implanting a first conductivity type implant species into a portion of the intermediate semiconductor layer underlying the first opening.
7. The method of claim 6 , further wherein forming the second non-MOS transistor device implant region includes forming a photoresist overlying the non-MOS transistor device portion and the CMOS electronic device portion, forming an opening within the photoresist over at least a portion of the second opening, and implanting a second conductivity type implant species into a portion of the intermediate semiconductor layer underlying the second opening.
8. The method of claim 1 , wherein forming the first low dose non-MOS transistor device well region includes implanting an implant species of a first conductivity type, and wherein forming the second low dose non-MOS transistor device well region includes implanting an implant species of a second conductivity type.
9. The method of claim 1 , further wherein forming the first low dose non-MOS transistor device well region includes forming a photoresist overlying the non-MOS transistor device portion and the CMOS electronic device portion, forming an opening within the photoresist over at least a first portion of the semiconductor layer disposed in-between the first and second openings in the non-MOS transistor device portion, and implanting a first conductivity type implant species into the first portion of the semiconductor layer disposed in-between the first and second openings.
10. The method of claim 1 , further wherein forming the second low dose non-MOS transistor device well region includes forming a photoresist overlying the non-MOS transistor device portion and the CMOS electronic device portion, forming an opening within the photoresist over at least a second portion of the semiconductor layer disposed in-between the first and second openings in the non-MOS transistor device portion, and implanting a second conductivity type implant species into the second portion of the semiconductor layer disposed in-between the first and second openings.
11. The method of claim 1 , wherein forming the first high dose non-MOS transistor device connectivity region includes implanting an implant species of the first conductivity type, and wherein forming the second high dose non-MOS transistor device contact region includes implanting an implant species of the second conductivity type.
12. The method of claim 1 , wherein forming the non-MOS transistor device liner comprises an oxidation process optimized to provide a lowest loss waveguide as a function of a reduction in sidewall roughness.
13. The method of claim 1 , wherein forming the trench liner comprises an oxidation process optimized to passivate the sidewalls, and to optimize a stress in the active semiconductor layer between the openings of the active semiconductor layer in the CMOS electronics device portion of the semiconductor substrate.
14. The method of claim 1 , wherein forming the salicide blocking layer comprises depositing TEOS on the non-MOS transistor device portion and the CMOS electronic device portion of the semiconductor substrate and then removing the TEOS from the CMOS electronic device portion and the portion of the non-MOS transistor device portion outside the region of the first and second low dose non-MOS transistor well regions.
15. The method of claim 1 , wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the at least the first and second low dose non-MOS transistor device well regions of the non-MOS transistor device portion of the semiconductor substrate.
16. The method of claim 1 , wherein saliciding includes forming a salicidation metallization overlying the non-MOS transistor device portion and the CMOS electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the CMOS electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the first and second low dose non-MOS transistor device well regions of the active semiconductor layer within the non-MOS transistor device portion of the semiconductor substrate.
17. The method of claim 1 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying a buried insulator; or (iii) a top semiconductor layer overlying a second semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, wherein the second semiconductor layer is lattice matched to the bottom semiconductor layer, and the bottom semiconductor layer overlying a buried insulator.
18. The method of claim 1 , wherein the fill material includes one or more of TEOS, a furnace oxide, or a high density plasma oxide.
19. The method of claim 1 , wherein the fill material comprises a material selected to provide a desired optical index of refraction.
20. The method of claim 19 , further wherein the optical index of refraction of the fill material is less than an optical index of refraction of silicon.
21. The method of claim 1 , wherein the portion of the CMOS electronic device comprises at least a gate dielectric and a gate electrode on the active semiconductor layer.
22. The method of claim 21 , wherein the portion of the CMOS electronic device further comprises sidewall spacers adjacent sidewalls of the gate electrode.
23. The method of claim 22 , wherein the portion of the CMOS electronic device further comprises source/drain regions proximate the gate electrode, gate dielectric, and sidewall spacers within the CMOS electronic device portion of the semiconductor substrate.