Granted Patent B2

US 7,384,819 · App. 11/414,440 · Granted Jun 10, 2008

Abstract

Claims (20)

1. A method of forming a plurality of stacked packages, comprising:

providing a plurality of substrates, each substrate having a die pad and a plurality of bond pads on a first surface thereof and a plurality of conductive pads on a second surface thereof;

attaching the first surfaces of the substrates to respective ones of a plurality of lead frames;

attaching a plurality of integrated circuit (IC) dice to the respective die pads on the first surfaces of the substrates;

electrically connecting the substrates, the respective lead frames and the respective IC dice;

encapsulating the IC dice, the electrical connections, a portion of the substrates and a portion of the lead frames with a mold compound, wherein the conductive pads on the second surfaces of the substrates are exposed, thereby forming a plurality of packaged devices;

attaching a plurality of semiconductor devices to respective ones of the second surfaces of the substrates, wherein the semiconductor devices are electrically connected to the respective IC dice by way of the conductive pads, thereby forming the stacked packages; and

separating the stacked packages from other ones of the stacked packages.

2. The method of forming a plurality of stacked packages of claim 1 , wherein the substrate provides electrical connection between the IC die and the at least one external semiconductor device.

3. The method of forming a plurality of stacked packages of claim 1 , wherein the plurality of semiconductor devices is electrically coupled to the conductive pads via one of a plurality of conductive balls and a plurality of leads.

4. The method of forming a plurality of stacked packages of claim 1 , wherein the plurality of semiconductor devices comprises one or more of a Quad Flat Pack (QEP) package, a Thin Small Outline Package (TSOP), a Small Outline Integrated Circuit (SOIC) package, a Small Outline J-Lead (SOJ) package, a Plastic Leaded Chip Carrier (PLCC) package, a Wafer Level Chip Scale Package (WLCSP), a Mold Array Process-Ball Grid Array (MAPBGA) package, a Quad Flat No-Lead (QFN) package, a Land Grid Array (LGA) package and a passive component.

5. The method of forming a plurality of stacked packages of claim 1 , further comprising encapsulating the plurality of semiconductor devices.

6. The method of forming a plurality of stacked packages of claim 1 , wherein each of the plurality of lead frames comprises:

a plurality of leads lying substantially in a first plane; and

a down-set portion coupled to respective ones of the leads, wherein the down-set portion lies in a second plane vertically spaced front the first plane.

7. The method of forming a plurality of stacked packages of claim 1 , further comprising the step of testing the packaged devices prior to attaching the semiconductor devices to the substrates.

8. The method of forming a plurality of stacked packages of claim 1 , wherein a film is attached to the second surface of each substrate.

9. The method of forming a plurality of stacked packages of claim 8 , further comprising removing the film from the second surfaces of each of the substrates to expose the conductive pads.

10. The method of forming a plurality of stacked packages of claim 1 , wherein the separation step comprises punch singulation.

11. The method of forming a plurality of stacked packages of claim 1 , wherein the substrates are provided by performing a singulating operation on a film laminated substrate.

Assignments (23)