IP Library Granted Patent US 7,282,307
Granted Patent B2
US 7,282,307 · App. 10/872,057 · Granted Oct 16, 2007

Reflective mask useful for transferring a pattern using extreme ultra violet (EUV) radiation and method of making the same

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Quick Facts
Patent No.
US 7,282,307
App. No.
10/872,057
Granted
Oct 16, 2007
Kind
B2
Abstract

An EUV mask ( 10, 309 ) includes an opening ( 26 ) that helps to attenuate and phase shift extreme ultraviolet radiation using a subtractive rather than additive method. A first embedded layer ( 20 ) and a second embedded layer ( 21 ) may be provided between a lower multilayer reflective stack ( 14 ) and an upper multilayer reflective stack ( 22 ) to ensure an appropriate and accurate depth of the opening ( 26 ), while allowing for defect inspection of the EUV mask ( 10, 309 ) and optional defect repair. An optional ARC layer ( 400 ) may be deposited in region ( 28 ) to reduce the amount of reflection within dark region ( 28 ). Alternately, a single embedded layer of hafnium oxide, zirconium oxide, tantalum silicon oxide, tantalum oxide, or the like, may be used in place of embedded layers ( 20, 21 ). Optimal thicknesses and locations of the various layers are described.

Claims (60)

1. A method for making a reflective mask useful for transferring a pattern to a semiconductor substrate comprising:

providing a mask substrate;

forming a lower multilayer reflective stack over the mask substrate;

forming a first embedded layer over the lower multilayer reflective stack;

forming a second embedded layer over the first embedded layer;

forming a top multilayer reflective stack over the second embedded layer; and

etching an opening through the top multilayer reflective stack to form an exposed portion of the second embedded layer,

wherein at least one of attenuation or phase shifting of incident radiation is achieved by way of destructive interference.

2. The method of claim 1 , further comprising removing the exposed portion of the second embedded layer.

3. The method of claim 2 , wherein removing the exposed portion of the second embedded layer comprises etching the exposed portion of the second embedded layer selective to the first embedded layer.

4. The method of claim 1 , wherein etching an opening further comprises forming a defect in the opening.

5. The method of claim 4 , further comprising:

inspecting the reflective mask after etching the opening through the top multilayer reflective stack; and

removing the defect in the opening.

6. The method of claim 1 , wherein forming the first embedded layer comprises forming a layer comprising a material selected from the group consisting of ruthenium, tantalum silicon oxide, boron carbide, hafnium oxide, zirconium oxide, zirconium and silicon oxynitride.

7. The method of claim 1 , wherein forming the second embedded layer comprises forming a layer comprising a material selected from the group consisting of chromium, chromium nitride, chromium oxide, hafnium oxide, zirconium oxide, zirconium and nickel iron.

8. The method of claim 1 , wherein forming the first embedded layer comprises forming a layer comprising a dielectric.

9. The method of claim 1 , wherein forming the first embedded layer and forming the second embedded layer comprise forming a layer comprising a material selected from hafnium oxide, zirconium oxide, tantalum silicon oxide and tantalum oxide.

10. The method of claim 1 , further comprising forming a third embedded layer over a second embedded layer.

11. A method for making a reflective mask useful for transferring a pattern to a semiconductor substrate comprising:

providing a mask substrate;

forming a lower multilayer reflective stack over the mask substrate;

forming a first embedded layer over the lower multilayer reflective stack; wherein the first embedded layer comprises a material selected from hafnium oxide, zirconium oxide, and tantalum oxide;

forming a top multilayer reflective stack over the first embedded layer; and

etching an opening through the top multilayer reflective stacks,

wherein at least one of attenuation or phase shifting of incident radiation is achieved by way of destructive interference.

12. The method of claim 11 , wherein etching an opening further comprises forming a defect in the opening.

13. The method of claim 12 , further comprising:

inspecting the reflective mask after etching the opening through the top multilayer reflective stack; and

removing the defect in the opening.

14. The method of claim 11 , further comprising forming a second embedded layer over the first embedded layer.

15. The method of claim 14 , wherein etching the opening through the top

multilayer reflective stack forms an exposed portion of the second embedded layer; and

wherein the method further comprises removing the exposed portion of the second embedded layer.

16. The method of claim 14 , wherein forming the second embedded layer comprises forming a layer comprising a material selected from the group consisting of chromium, chromium nitride, chromium oxide, hafnium oxide, zirconium oxide, zirconium and nickel iron.

17. The method of claim 14 , further comprising a third embedded layer over the second embedded layer.

18. A method for patterning a photoresist layer on a semiconductor substrate using a reflective mask comprising:

providing a semiconductor substrate;

forming a photoresist layer over the semiconductor substrate;

providing a reflective mask, the reflective mask comprising:

a mask substrate;

a lower multilayer reflective stack formed over the mask substrate;

a top multilayer reflective stack over the lower multilayer reflective stack, wherein the top multilayer reflective stack includes an opening;

a first embedded layer under the top multilayer reflective stack and exposed in the opening; and

a second embedded layer under the top multilayer reflective stack;

projecting incident radiation on the reflective mask,

wherein at least one of attenuation or phase shifting of the incident radiation is achieved by way of destructive interference;

reflecting the incident radiation from the reflective mask as reflected radiation; and illuminating the photoresist layer with the reflected radiation.

19. The method of claim 18 , the first embedded layer comprises forming a layer comprising a material selected from the group consisting of ruthenium, tantalum silicon oxide, boron carbide, hafnium oxide, zirconium oxide, zirconium and silicon oxynitride.

20. The method of claim 19 , wherein the second embedded layer comprises forming a layer comprising a material selected from the group consisting of chromium, chromium nitride, chromium oxide, hafnium oxide, zirconium oxide, zirconium and nickel iron.

21. The method of claim 18 , wherein the first embedded layer comprises a dielectric.

22. The method of claim 18 , wherein the first embedded layer and the second embedded layer comprise a material selected from the group consisting of hafnium oxide, zirconium oxide, tantalum silicon oxide and tantalum oxide.

23. The method of claim 18 , wherein the reflective mask further comprises a third embedded layer over the second embedded layer.

24. A reflective mask comprising:

a mask substrate;

a lower multilayer reflective stack formed over the mask substrate;

a top multilayer reflective stack over the lower multilayer reflective stack, wherein the top multilayer reflective stack includes an opening;

a first embedded layer under the top multilayer reflective stack and exposed in the opening; and

a second embedded layer under the top multilayer reflective stack,

wherein a thickness of the second embedded layer is selected to produce at least one of attenuation or phase shifting of incident radiation by way of destructive interference.

Assignments (23)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0670 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Jul 11, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021217/0368 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 18, 2004
From: HECTOR, SCOTT D.; HAN, SANG-IN
To: FREESCALE SEMICONDUCTOR, INC.
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