Binary stream switching controlled modulus divider for fractional frequency synthesis
View Patent ↗A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, is provided. The modulus divider controller may further include a first binary stream switching circuit having a first output and a second output. The first binary stream switching circuit may further have a logic low input and a logic high input and a first switching input corresponding to a most significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock. The first binary stream switching circuit may further have a second switching input corresponding to a least significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock.
1. A modulus divider controller coupled to a modulus divider for generating a synthesized clock from a reference clock, wherein the modulus divider generates a divided clock, the modulus divider controller comprising:
a first binary stream switching circuit having a first output and a second output, the first binary stream switching circuit further having a logic low input and a logic high input and a first switching input corresponding to a least significant bit of a count generated by a synchronous counter, wherein the synchronous counter counts the divided clock, and a second switching input corresponding to a most significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock; and
a second binary stream switching circuit having the first output of the first binary stream switching circuit as a first input and the second output of the first binary stream switching circuit as a second input, the second binary stream switching circuit further having a first switching input corresponding to a bit next to the least significant bit of the count generated by the synchronous counter and a second switching input corresponding to a bit next to the most significant bit of the division control word, wherein the second binary stream switching circuit generates a modulus control output for the modulus divider based on the first input, the second input, the first switching input, and the second switching input corresponding to the second binary stream switching circuit.
2. The modulus divider controller of claim 1 further comprising a first buffer for delaying a signal corresponding to the first switching input of the first binary stream switching circuit.
3. The modulus divider controller of claim 2 further comprising a second buffer for delaying a signal corresponding to the second switching input.
4. The modulus divider controller of claim 3 , wherein the first buffer delays the signal corresponding to the first switching input and the second buffer delays the signal corresponding to the second switching input such that they are synchronized in time with respect to other inputs.
5. The modulus divider controller of claim 1 , wherein the first binary stream switching circuit generates a modulus control output corresponding to logic low when the first switching input and the second switching input are each logic low.
6. The modulus divider controller of claim 1 , wherein the first binary stream switching circuit generates a modulus control output corresponding to logic low when the first switching input is logic low and the second switching input is logic high.
7. The modulus divider controller of claim 1 , wherein the first binary stream switching circuit generates a modulus control output corresponding to logic low when the first switching input is logic high and the second switching input is logic low.
8. The modulus divider controller of claim 1 , wherein the first binary stream switching circuit generates a modulus control output corresponding to logic high when the first switching input and the second switching input are each logic high.
9. The modulus divider controller of claim 1 , wherein the modulus control output is received as an input for a modulus divider.
10. The modulus divider controller of claim 9 , wherein the input for the modulus divider determines whether the synthesized clock is divided by N or N+1.
11. A method for generating a synthesized clock from a reference clock using a modulus divider, the method comprising:
receiving a pair of inputs and a logic low input and a logic high input;
receiving a first switching input corresponding to a least significant bit of a count generated by a synchronous counter that counts a divided clock; receiving a second switching input corresponding to a most significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock;
generating a first output and a second output based on the logic low input, the logic high input, and the first switching input; and
generating a modulus divider control output based on the first output, the second output, at least one other switching input corresponding to at least one other bit of the count, and at least one other switching input corresponding to at least one other bit of the division control word.
12. The method of claim 11 further comprising receiving the modulus divider control output at a modulus divider and dividing the synthesized clock by N or N+1 based on the modulus divider control output to generate a divided clock.
13. The method of claim 12 further comprising feeding back the divided clock to an input of a phase frequency detector.
14. The method of claim 13 further comprising comparing the divided clock to a reference clock to generate a voltage signal and inputting the voltage signal to a voltage controlled oscillator.
15. An apparatus for generating a synthesized clock from a reference clock using a modulus divider, the apparatus comprising:
means for receiving a pair of inputs and a logic low input and a logic high input;
means for receiving a first switching input corresponding to a least significant bit of a count generated by a synchronous counter that counts a divided clock; means for receiving a second switching input corresponding to a most significant bit of a division control word, wherein the division control word specifies a fractional division ratio for the synthesized clock;
means for generating a first output and a second output based on the logic low input, the logic high input, and the first switching input; and
means for generating a modulus divider control output based on the first output, the second output, at least one other switching input corresponding to at least one other bit of the count, and at least one other switching input corresponding to at least one other bit of the division control word.
16. The apparatus of claim 15 further comprising means for dividing the synthesized clock by N or N+1 based on the modulus divider control output to generate a divided clock.
17. The apparatus of claim 15 further comprising means for comparing the divided clock to a reference clock to generate a voltage signal.