Storage circuit and method therefor
View Patent ↗Storage circuits ( 180 - 183 and 280 - 281 ) may be used for low power operation while allowing fast read access. In one embodiment (e.g. circuit 100 ), shared complementary write bit lines ( 101, 102 ), separate read bit lines ( 103 - 106 ), a shared read word line ( 107 ), and separate write word lines ( 108 - 111 ) are used. In an alternate embodiment (e.g. circuit 200 ), shared complementary write bit lines ( 201, 202 ), a shared read bit line ( 203 ), separate read word lines ( 206 - 207 ), and separate write word lines ( 208 - 209 ) are used. The storage circuit may be used in a variety of contexts, such as, for example, a register file ( 17 ), a branch unit ( 15 ), an SRAM ( 19 ), other modules ( 20 ), a cache ( 18 ), a buffer ( 21 ), and/or a memory ( 14 ).
1. A storage circuit comprising:
a first storage cell having a first terminal and a second terminal for storing a first data value;
a second storage cell having a first terminal and a second terminal for storing a second data value;
a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively,
wherein the first data value and the second data value are non-concurrently writable;
a first read bit line coupled to the first storage cell for selectively reading only the first storage cell; and
a second read bit line coupled to the second storage cell for selectively reading only the second storage cell.
2. The storage circuit of claim 1 further comprising:
a shared read word line for selectively enabling reading each of the first storage cell and second storage cell in response to a shared read signal.
3. The storage circuit of claim 1 wherein the first storage cell and the second storage cell each comprise one of a static random access memory (SRAM) cell, a register, a cache tag array memory cell, a buffer or a branch unit memory cell.
4. The storage circuit of claim 1 further comprising:
a first select gate coupled to the first terminal of the first storage cell;
a second select gate coupled to the second terminal of the second storage cell;
a first write word line coupled to the first select gate, the first write word line enabling the first select gate to write the first storage cell;
a second write word line coupled to the second select gate, the second write word line enabling the second select gate to write the second storage cell.
5. The storage circuit of claim 4 further comprising:
a third select gate coupled to the second terminal of the first storage cell, the third select gate being controlled by the first write word line; and
a fourth select gate coupled to the first terminal of the second storage cell, the fourth select gate being controlled by the second write word line.
6. The storage circuit of claim 1 wherein the first storage cell is assigned to a first way of an associative memory and the second storage cell is assigned to a second way of the associative memory.
7. A storage circuit comprising:
a first storage cell having a first terminal and a second terminal for storing a first data value;
a second storage cell having a first terminal and a second terminal for storing a second data value;
a first write word line coupled to the first storage cell for selectively writing to only the first storage cell;
a second write word line coupled to the second storage cell for selectively writing to only the second storage cell;
a first select gate coupled to the first storage cell and a second select gate coupled to the second storage cell;
a shared read word line coupled to each of the first select gate and the second select gate for selectively providing a control signal to provide both the first data value and the second data value from the first storage cell and the second storage cell, respectively.
8. The storage circuit of claim 7 further comprising:
a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively.
9. A storage circuit comprising:
a first storage cell having a first terminal and a second terminal for storing a first data value;
a second storage cell having a first terminal and a second terminal for storing a second data value;
a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively;
a first read select gate for selectively enabling reading the first storage cell and a second read select gate for selectively enabling reading the second storage cell; and
a shared read bit line coupled to each of the first read select gate and the second read select gate for selectively reading each of the first storage cell and the second storage cell.
10. The storage circuit of claim 9 wherein at least one of the shared write bit line and the shared read bit line further comprises a complementary bit line selectively affecting or affected by one of the first terminal or the second terminal of the first storage cell and the second storage.
11. The storage circuit of claim 9 further comprising:
a first write word line coupled to the first storage cell and a second write word line coupled to the second storage cell for selectively separately writing the first storage cell and the second storage cell; and
a first read word line coupled to the first storage cell and a second read word line coupled to the second storage cell for selectively separately reading the first storage cell and the second storage cell.
12. A storage circuit comprising:
a first storage cell having a first terminal and a second terminal for storing a first data value;
a second storage cell having a first terminal and a second terminal for storing a second data value;
a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively;
a first read bit line coupled to the first storage cell for selectively reading only the first storage cell;
a second read bit line coupled to the second storage cell for selectively reading only the second storage cell;
a first select gate coupled to the first terminal of the first storage cell;
a second select gate coupled to the second terminal of the second storage cell;
a first write word line coupled to the first select gate, the first write word line enabling the first select gate to write the first storage cell; and
a second write word line coupled to the second select gate, the second write word line enabling the second select gate to write the second storage cell.
13. A storage circuit comprising:
a first storage cell having a first terminal and a second terminal for storing a first data value;
a second storage cell having a first terminal and a second terminal for storing a second data value;
a shared write bit line coupled to each of the first storage cell and the second storage cell for selectively providing both the first data value and the second data value to the first storage cell and the second storage cell, respectively;
a first read bit line coupled to the first storage cell for selectively reading only the first storage cell;
a second read bit line coupled to the second storage cell for selectively reading only the second storage cell;
a first select gate coupled to the first terminal of the first storage cell;
a second select gate coupled to the second terminal of the second storage cell;
a first write word line coupled to the first select gate, the first write word line enabling the first select gate to write the first storage cell;
a second write word line coupled to the second select gate, the second write word line enabling the second select gate to write the second storage cell;
a third select gate coupled to the second terminal of the first storage cell, the third select gate being controlled by the first write word line; and
a fourth select gate coupled to the first terminal of the second storage cell, the fourth select gate being controlled by the second write word line.