Granted Patent B2

US 7,528,078 · App. 11/433,298 · Granted May 5, 2009

Abstract

Claims (70)

1. A process of forming an electronic device comprising:

patterning a semiconductor layer to define an opening extending to an insulating layer,

wherein the insulating layer lies between a substrate and the semiconductor layer,

wherein after patterning the semiconductor layer:

the opening has a bottom;

the semiconductor layer has a sidewall and a surface;

the surface is spaced apart from the insulating layer; and

the sidewall extends from the surface towards the insulating layer;

depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique;

densifying the nitride layer; and

removing a part of the nitride layer using an oxide etchant, wherein after removing the part of the nitride layer, a remaining portion of the nitride layer lies within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the nitride layer is spaced apart from the surface, and wherein removing the part of the nitride layer comprises removing the part of the nitride layer that lies outside the opening in the semiconductor layer.

2. The process of claim 1 , wherein removing the part of the nitride layer comprises removing the part of the nitride layer, wherein, as seen from a cross-sectional view, the remaining portion has an extended portion, wherein the extended portion:

lies adjacent to the sidewall of the semiconductor layer; and

has a highest elevation that lies above a center elevation of the remaining portion at a center of the opening and below a surface elevation of the surface of the semiconductor layer, wherein each of the highest elevation, the center elevation, and the surface elevation is measured from a primary surface of the substrate.

3. The process of claim 1 , wherein:

the semiconductor layer has a first thickness; and

depositing the nitride layer comprises depositing the nitride layer to a second thickness in a range of approximately 5% to approximately 50% of the first thickness.

4. The process of claim 3 , wherein depositing the nitride layer comprises depositing the nitride layer to the second thickness in a range of approximately 20% to approximately 40% of the first thickness.

5. The process of claim 1 , wherein densifying the nitride layer is performed at a temperature of at least approximately 800° C.

6. The process of claim 5 , wherein densifying the nitride layer is performed at the temperature in a range of approximately 1000° C. to approximately 1200° C.

7. The process of claim 6 , wherein densifying the nitride layer is performed using an ambient consisting essentially of a noble gas.

8. The process of claim 6 , wherein densifying the nitride layer is performed for a time period no greater than approximately 60 minutes.

9. The process of claim 1 , wherein removing the part of the nitride layer is performed using a solution comprising HF.

10. The process of claim 9 , wherein removing the part of the nitride layer is performed using the solution, wherein:

the solution has an oxide etch rate in a range of approximately 1 to approximately 4 nm/minute; and

the nitride layer is exposed to the solution for a time period in a range of approximately 5 to approximately 20 minutes.

11. The process of claim 1 , further comprising oxidizing the semiconductor layer, wherein:

the semiconductor layer includes a first corner and a second corner;

the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;

the first corner becomes rounded during oxidizing the semiconductor layer; and

the second corner substantially maintains its shape during oxidizing the semiconductor layer.

12. The process of claim 11 , further comprising:

depositing an oxide layer that substantially fills a rest of the opening; and

polishing the oxide layer to remove a portion of the oxide layer lying outside the opening.

13. The process of claim 12 , further comprising:

forming a patterned oxidation-resistant layer over the semiconductor layer before patterning the semiconductor layer; and

removing the patterned oxidation-resistant layer after polishing the oxide layer.

14. The process of claim 11 , further comprising forming a gate dielectric layer adjacent to the surface and the first corner of the semiconductor layer.

15. The process of claim 14 , further comprising forming a gate electrode, wherein:

the gate dielectric layer lies between the semiconductor layer and the gate electrode; and

the gate electrode lies adjacent to the surface and the first corner of the semiconductor layer.

16. The process of claim 1 , wherein patterning the semiconductor layer comprises patterning the semiconductor layer, wherein the semiconductor layer comprises germanium.

17. A process of forming an electronic device comprising:

forming a patterned oxidation-resistant layer over a semiconductor layer, wherein an insulating layer lies between a substrate and the semiconductor layer;

patterning the semiconductor layer to define an opening extending to the insulating layer, wherein after patterning the semiconductor layer:

the opening has a bottom;

the semiconductor layer has a sidewall and a surface;

the surface is spaced apart from the insulating layer; and

the sidewall extends from the surface towards the insulating layer;

depositing a nitride layer within the opening, wherein depositing is performed using a PECVD technique;

densifying the nitride layer;

exposing the nitride layer to a solution including HF, wherein after exposing the nitride layer to the solution, a remaining portion of the nitride layer lies within the opening and adjacent to the bottom and the sidewall, and the remaining portion of the nitride layer is spaced apart from the surface;

oxidizing the semiconductor layer after exposing the nitride layer to the solution;

depositing an oxide layer that substantially fills a rest of the opening;

polishing the oxide layer to remove a portion of the oxide layer lying outside the opening;

removing the patterned oxidation-resistant layer after polishing the oxide layer;

forming a gate dielectric layer adjacent to the surface of the semiconductor layer; and

forming a gate electrode, wherein the gate dielectric layer lies between the semiconductor layer and the gate electrode.

18. The process of claim 17 , wherein densifying the nitride layer is performed:

at a temperature in a range of approximately 1000° C. to approximately 1200° C.;

for a time period in a range of approximately 5 to approximately 60 minutes; and

using an ambient including argon.

19. The process of claim 17 , wherein removing the part of the nitride layer is performed using the solution, wherein:

the solution has an oxide etch rate in a range of approximately 1 to approximately 4 nm/minute; and

the nitride layer is exposed to the solution for a time in a range of approximately 5 to approximately 20 minutes.

20. The process of claim 17 , wherein oxidizing the semiconductor layer is performed such that:

the semiconductor layer includes a first corner and a second corner;

the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;

the first corner becomes rounded during oxidizing the semiconductor layer; and

the second corner substantially maintains its shape during oxidizing the semiconductor layer.

Assignments (31)