IP Library Granted Patent US 7,420,401
Granted Patent B2
US 7,420,401 · App. 11/453,324 · Granted Sep 2, 2008

Low pin count reset configuration

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,420,401
App. No.
11/453,324
Granted
Sep 2, 2008
Kind
B2
Abstract

An integrated circuit is configured with a pin for specifying a reset configuration vector of a circuitry within the integrated circuit. The resistance value of a low cost external resistor coupled to the pin is detected and utilized to identify the configuration. Logic on the integrated circuit detects and utilizes the resistor value to index to a configuration vector in a look-up table. The integrated circuit is then configured in accordance with the indexed configuration vector.

Claims (73)

1. A system comprising:

a configurable integrated circuit with a configuration pin; and

a circuit connected to the configuration pin capable of generating a reference current or voltage with a predictable voltage/current relationship based on a resistance value coupled to the configuration pin; and

a resistor value detection circuit for determining a look-up table index value in response to the reference current or voltage, wherein the resistor value detection circuit includes:

a reference up-counter configured to be clocked at a reference clock frequency;

a down-counter configured to be clocked at a frequency of the reference current or voltage; and

counter control logic circuitry.

2. The system of claim 1 , where the circuit connected to the configuration pin capable of generating a reference current or voltage with a predictable voltage/current relationship comprises:

a current controlled oscillator.

3. The system of claim 1 , wherein the configurable integrated circuit comprises:

a look-up table for associating a configuration vector for the configurable integrated circuit with the reference current or voltage.

4. The system of claim 1 , wherein the counter control logic circuitry comprises logic that is configured to:

initialize the down-counter,

initialize the reference up-counter,

clock the down-counter,

clock the reference up-counter, and

disable the clocking of the reference up-counter when the down-counter reaches a termination value.

5. The system of claim 1 , where the configurable integrated circuit initializes to a configuration vector associated with the reference current or voltage in response to a power-on-reset signal.

6. The system of claim 1 , where the configuration vector indicates at least one of input/output bus port width and pad drive strength.

7. A configurable integrated circuit comprising:

a configuration input pin for coupling to an external resistance element;

a circuit capable of generating a reference current or voltage with a predictable voltage/current relationship connected to the configuration input pin; and

resistor value detection logic for determining an index value associated with the external resistance element, wherein the resistor value detection logic includes:

a reference up-counter operating at a reference clock frequency;

a down-counter operating at a frequency of a resistor clock; and

counter control logic circuit.

8. The configurable integrated circuit of claim 7 , where the circuit comprises:

a current controlled oscillator.

9. The configurable integrated circuit of claim 7 , said configurable integrated circuit further comprising a look-up table for associating the index value of the external resistor with a configuration vector, wherein the configurable integrated circuit is responsive to the configuration vector to configure operation.

10. The configurable integrated circuit of claim 9 , where the configuration vector indicates at least one of input/output bus port width and pad drive strength.

11. The configurable integrated circuit of claim 7 , wherein the counter control logic is configured to:

initialize the down-counter,

initialize the reference up-counter,

enable the down-counter,

enable the reference up-counter; and

disable the reference up-counter when the down-counter reaches a termination value.

12. The configurable integrated circuit of claim 7 , where the integrated circuit initializes to a configuration vector associated with the reference current or voltage in response to a power-on-reset signal.

13. A method for configuring an integrated circuit with a configuration vector, wherein the integrated circuit stores a plurality of configuration vector and includes a configuration pin coupled to an external resistor selected based on a desired operational configuration of the integrated circuit, said method comprising the steps of:

determining an external resistor value of the external resistor, wherein said determining an external resistor value of the external resistor comprises:

(a) initializing a down-counter;

(b) initializing a reference up-counter;

(c) enabling the down-counter;

(d) enabling the reference up-counter;

(e) incrementing the reference up-counter while the down-counter is not equal to a termination value; and

(f) disabling the reference up-counter when the down-counter reaches the termination value; and

setting a configuration of the integrated circuit to a configuration vector from among the plurality of configuration vectors that is associated with the external resistor value to place the integrated circuit in the desired operational configuration.

14. The method for configuring the integrated circuit of claim 13 , said method further comprising:

converting the external resistor value into an index value suitable for indexing into a plurality of configuration value and index value pairs.

15. The method for configuring the integrated circuit of claim 14 , wherein the plurality of configuration value and index value pairs is a table and the index value is an index into the table, said method further comprising:

converting a count of the reference up-counter into the index value.

16. The method for configuring the integrated circuit of claim 13 , wherein the step of determining the external resistor value comprises:

decrementing the down-counter at a frequency of a resistor clock output from a current controlled oscillator controlled as a function of the external resistor value.

17. The method for configuring the integrated circuit of claim 13 , wherein the step of determining the external resistor value takes place in response to a power-on-reset signal.

18. The method for configuring the integrated circuit of claim 13 , where the configuration vector indicates at least one of input/output bus port width and pad drive strength.

19. A configurable integrated circuit comprising:

a configuration input pin for coupling to an external resistance element;

a circuit connected to the configuration pin capable of generating a reference current or voltage with a predictable voltage/current relationship in response to the external resistance element; and

resistor value detection logic responsive to the reference current or voltage to determine a configuration vector associated with an external resistance element coupled to the configuration input pin, wherein the resistor value detection logic includes:

a reference up-counter operating at a reference clock frequency;

a down-counter operating at a frequency associated with the reference current or voltage; and

a counter control logic circuit;

wherein the configurable integrated circuit is responsive to the configuration vector to configure operation.

20. The configurable integrated circuit of claim 19 , where the circuit comprises:

a current controlled oscillator.

21. The configurable integrated circuit of claim 19 , wherein said resistor value detection logic is responsive to the reference current or voltage to generate an index value associated with the external resistor, and further comprising a look-up table for associating the index value of the external resistor with a configuration vector, wherein the configurable integrated circuit is responsive to the configuration vector to configure operation.

22. The configurable integrated circuit of claim 19 , where the configuration vector indicates at least one of input/output bus port width and pad drive strength.

23. The configurable integrated circuit of claim 19 , wherein the counter control logic is configured to:

initialize the down-counter,

initialize the reference up-counter,

enable the down-counter,

enable the reference up-counter; and

disable the reference up-counter when the down-counter reaches a termination value.

24. The configurable integrated circuit of claim 19 where the integrated circuit initializes to a configuration vector associated with the external resistance element in response to a power-on-reset signal.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2006
From: MACDONALD, COLIN; CARLIN, ALAN J.; DAO, CHRIS C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017981/0846 →