Timer unit, system, computer program product and method for testing a logic circuit
View Patent ↗A timer unit includes a timer for timing the period of time the logic circuit has been in the self-test mode. A comparator is connected to the timer, for comparing the period of time with a maximum for the period of time the logic circuit is allowed to be in the self-test mode and outputting an error signal when the period of time exceeds the maximum. The test timer unit further includes a mode detector for detecting a switching of the logic circuit to the self-test mode. The mode detector is connected to the timer, for starting the timer upon the switching to the self-test mode and stopping the timer upon a switching of the logic circuit out of the self-test mode. The timer unit can be used in a system for testing a logic circuit which includes a test routine module containing a set of instructions which forms a test routine for performing a test on a tested part of the logic circuit. The system has a mode control unit containing a set of instructions which is executable by the logic circuit, for switching the logic circuit from and to a test mode in which a part of the logic circuit can be subjected to a selected test by executing a selected test routine.
1. A timer unit for measuring a period of time of an operation of a logic circuit comprising:
a timer for measuring the period of time said logic circuit has been in a non-normal mode different from a normal operation mode;
a comparator connected to said timer, for comparing said measured period of time with a maximum for the period of time said logic circuit is allowed to be in said non-normal mode and outputting an error signal signifying a fault in operation of the logic circuit in the non-normal mode when said measured period of time exceeds said maximum; and
a mode detector for detecting a switching of said logic circuit from a normal operation mode to said non-normal mode, said mode detector being connected to said timer, for automatically starting said timer upon a detection of a switching of said logic circuit to said non-normal mode and automatically stopping said timer upon a detection of a switching of said logic circuit out of said non-normal mode.
2. A timer unit as claimed in claim 1 , including a timer controller connected to said mode detector and said timer, for resetting the stopped timer or setting said maximum, such that the period of time indicated by said stopped timer is the same as, or exceeds, said maximum.
3. A timer unit as claimed in claim 2 , wherein said timer controller sets, when said logic circuit is switched to the non-normal mode, said timer and/or said maximum such that the difference between the period of time indicated by said timer and said maximum corresponds to the period of time said logic circuit is allowed to be in said non-normal mode.
4. A timer unit as claimed in claim 2 , wherein the resetting the timer or setting the maximum is not permitted in the non-normal mode.
5. A timer unit as claimed in claim 2 , wherein said comparator compares the period of time indicated by the stopped timer with a minimum for the duration of an operation to be performed in said non-normal mode, and outputs an error signal in case the period of time indicated by the stopped timer is less than the minimum, wherein the minimum and the maximum are two different values.
6. A timer unit as claimed in claim 2 , implemented as a hardware device connectable to said logic circuit.
7. A timer unit as claimed in claim 2 , wherein said non-normal mode includes one or more of: a low power mode, interrupt mode, idle mode.
8. A timer unit as claimed in claim 1 , wherein said comparator compares the period of time indicated by the stopped timer with a minimum for the duration of an operation to be performed in said non-normal mode, and outputs an error signal in case the period of time indicated by the stopped timer is less than the minimum.
9. A timer unit as claimed in claim 1 , implemented as a hardware device connectable to said logic circuit.
10. A timer unit as claimed in claim 1 , wherein said non-normal mode includes one or more of: a low power mode, interrupt mode, idle mode.
11. A system for testing a logic circuit, said system comprising:
at least one test routine module containing a set of instructions forming a test routine for performing a test on a tested part of said logic circuit;
a mode control unit containing a set of instructions for switching said logic circuit from and to a test mode in which at least one part of said logic circuit can be subjected to at least one selected test by executing at least one selected test routine; and
a test timer unit as claimed in claim 1 .
12. A system as claimed in claim 11 , wherein at least one of said test routines is a self-test routine executable by at least one self-testing part of said logic circuit.
13. A system as claimed in claim 12 , wherein said logic circuit is part of one or more of the group consisting of: a microprocessor, a central processing unit, a microcontroller, a digital signal processor.
14. A system as claimed in claim 12 , wherein said logic circuit is arranged to execute a control application for controlling the operation of at least one actuator.
15. A system as claimed in claim 11 , wherein said logic circuit is part of one or more of the group consisting of: a microprocessor, a central processing unit, a microcontroller, a digital signal processor.
16. A system as claimed in claim 15 , wherein said logic circuit is a processor core.
17. A system as claimed in claim 11 , wherein said logic circuit is arranged to execute a control application for controlling the operation of at least one actuator.
18. An assembly of a logic circuit and a system as claimed in claim 11 .
19. A timer unit as claimed in claim 1 , wherein said mode detector is to detect the switching of said logic circuit to said non-normal mode by monitoring one or more of:
a register or other part of the logic circuit in which data is stored when the logic circuit is brought into said non-normal mode;
locations in a memory in which the logic circuit saves its internal state upon entry into said non-normal mode; and
whether or not parts of the logic circuit turned off in said non-normal mode are switched off.
20. A method for testing at least a part of a logic circuit, including:
switching said logic circuit to a test mode in which at least one tested part said logic circuit can be subjected to at least one selected test;
performing said at least one selected test by at least one tested part of said logic circuit;
switching said logic circuit out of said test mode after completion of the at least one selected test routine; and
executing a test timing procedure including:
detecting a switching of said logic circuit to said test mode;
starting a timer in response to said detecting, for timing the period of time said logic circuit has been in said test mode;
comparing said period of time with a maximum for the period of time said logic circuit is allowed to be in said test mode; and
outputting an error signal when said period of time exceeds said maximum; and comparing the period of time indicated by the stopped timer with a minimum for the duration of an operation to be performed in said non-normal mode, and outputting an error signal in case the period of time indicated by the stopped timer is less than the minimum.