Process of forming an electronic device including a layer formed using an inductively coupled plasma
View Patent ↗A process of forming an electronic device can include patterning a semiconductor layer to define an opening extending to an insulating layer, wherein the insulating layer lies between a substrate and the semiconductor layer. After patterning a semiconductor layer, the semiconductor layer can have a sidewall and a surface, the surface can be spaced apart from the insulating layer, and the sidewall can extend from the surface towards the insulating layer. The process can also include chemical vapor depositing a first layer adjacent to the sidewall, wherein the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface. Chemical vapor depositing the first layer can be performed using an inductively coupled plasma.
1. A process of forming an electronic device comprising:
patterning a semiconductor layer to define an opening extending to an insulating layer,
wherein the insulating layer lies between a substrate and the semiconductor layer,
wherein after patterning the semiconductor layer:
the semiconductor layer has a sidewall and a surface;
the surface is spaced apart from the insulating layer; and
the sidewall extends from the surface towards the insulating layer; and chemical vapor depositing a first layer adjacent to the sidewall, wherein:
the first layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface; and
chemical vapor depositing the first layer is performed:
using an inductively coupled plasma;
at a pressure no greater than approximately 20 mTorr;
using a chamber that is coupled to a biasing power supply and an ionizing power supply; and
during chemical vapor depositing, the biasing power supply provides a first power to the chamber at a first power flux no greater than approximately 1.6 watts/cm 2 , and the ionizing power supply provides a second power to the chamber at a second power flux that is more than double the first power flux.
2. The process of claim 1 , wherein during chemical vapor depositing:
the biasing power supply provides the first power at a first frequency;
the ionizing power supply provides the second power at a second frequency; and
the first frequency is higher than the second frequency.
3. The process of claim 2 , wherein chemical vapor depositing comprises chemical vapor depositing using He as an only noble gas.
4. The process of claim 1 , wherein during chemical vapor depositing:
the first power flux is substantially 0 watts/cm 2 ; and
the second power flux is in a range of approximately 3.2 watt/cm 2 to approximately 16 watt/cm 2 .
5. The process of claim 1 , wherein chemical vapor depositing comprises chemical vapor depositing the first layer along a bottom of the opening and along the sidewall at a first point adjacent to the insulating layer, but not along the sidewall at a second point adjacent to the surface.
6. The process of claim 1 , further comprising oxidizing the semiconductor layer, wherein:
the semiconductor layer includes a first corner and a second corner;
the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;
the first corner becomes rounded during oxidizing the semiconductor layer; and
the second corner substantially maintains its shape during oxidizing the semiconductor layer.
7. The process of claim 6 , wherein oxidizing the semiconductor layer comprises thermally growing an oxide layer from the semiconductor layer, wherein the oxide layer has a thickness less than approximately 20 nm.
8. The process of claim 6 , wherein oxidizing the semiconductor layer comprises thermally growing an oxide layer from the semiconductor layer, wherein the oxide layer has a thickness in a range of approximately 6 to approximately 10 nm.
9. The process of claim 6 , wherein oxidizing the semiconductor layer is performed using an ambient including O 2 and HCl at a temperature in a range of approximately 800° C. to approximately 1150° C.
10. The process of claim 6 , further comprising:
depositing an insulating layer that substantially fills the opening; and
polishing the insulating layer to remove a portion of the insulating layer lying outside the opening.
11. The process of claim 10 , further comprising:
forming a patterned oxidation-resistant layer over the semiconductor layer before patterning the semiconductor layer; and
removing the patterned oxidation-resistant layer after polishing the insulating layer.
12. The process of claim 1 , wherein chemical vapor depositing the first layer comprises chemical vapor depositing a nitride layer.
13. The process of claim 1 , wherein chemical vapor depositing comprises chemical vapor depositing using feed gases including:
a Si y H 2 X 2y+2−z , wherein:
X is a halogen (F, Cl, Br, I, or any combination thereof);
y is an integer having a value from 1 to 3; and
z is an integer having a value from 0 to 2y+2; and
N 2 , NH 3 , N 2 H 4 , or any combination thereof.
14. The process of claim 13 , wherein chemical vapor depositing comprises chemical vapor depositing using the feed gases that further include He.
15. The process of claim 1 , further comprising:
forming a gate dielectric layer adjacent to the surface and the first corner of the semiconductor layer; and
forming a gate electrode, wherein:
the gate dielectric layer lies between the semiconductor layer and the gate electrode; and
the gate electrode lies adjacent to the surface and the first corner of the semiconductor layer.
16. A process of forming an electronic device comprising:
forming a patterned oxidation-resistant layer over a semiconductor layer, wherein an insulating layer lies between a substrate and the semiconductor layer;
patterning the semiconductor layer to define an opening extending to the insulating layer, wherein after patterning the semiconductor layer:
the semiconductor layer has a sidewall and a surface;
the surface is spaced apart from the insulating layer; and
the sidewall extends between the insulating layer and the surface;
chemical vapor depositing a nitride layer, wherein:
the nitride layer lies within the opening and adjacent to the sidewall, and is spaced apart from the surface; and
chemical vapor depositing is performed using a chamber that is coupled to a biasing power supply and an ionizing power supply, wherein during chemical vapor depositing:
the biasing power supply provides substantially no power to the chamber; and
the ionizing supply provides a power greater than 0 watts to the chamber;
oxidizing the semiconductor layer after chemical vapor depositing the nitride layer, wherein:
the semiconductor layer includes a first corner and a second corner;
the first corner is adjacent to the surface, and the second corner is adjacent to the insulating layer;
the first corner becomes rounded during oxidizing the semiconductor layer; and
the second corner substantially maintains its shape during oxidizing the semiconductor layer;
depositing an oxide layer that substantially fills the opening;
polishing the oxide layer to remove a portion of the oxide layer lying outside the opening;
removing the patterned oxidation-resistant layer after removing the portion of the oxide layer;
forming a gate dielectric layer adjacent to the semiconductor layer; and
forming a gate electrode, wherein:
the gate dielectric layer lies between the semiconductor layer and the gate electrode; and
the gate dielectric layer and the gate electrode are part of an n-channel transistor.
17. The process of claim 16 , wherein chemical vapor depositing is performed using feed gases including SiH 4 , N 2 , and He.
18. The process of claim 16 , wherein chemical vapor depositing the nitride layer is performed using an inductively coupled plasma.
19. The process of claim 16 , wherein chemical vapor depositing the nitride layer is performed:
at a pressure no greater than about 20 mTorr;
such that the ionizing supply provides the power in a range of approximately 3000 watts to approximately 5000 watts;
using He as an only noble gas; and
such that the nitride layer is formed to a thickness that is approximately 33% to approximately 80% of a thickness of the semiconductor layer.