IP Library › Granted Patent US 7,067,342

Granted Patent B2

US 7,067,342 · App. 10/988,963 · Granted Jun 27, 2006

Method of integrating optical devices and electronic devices on an integrated circuit

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Quick Facts

Patent No.: US 7,067,342
App. No.: 10/988,963
Granted: Jun 27, 2006
Kind: B2

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Abstract

A semiconductor structure has a waveguide a transistor on the same integrated circuit. One trench isolation technique is used for defining a transistor region and another is used for optimizing a lateral boundary of the waveguide. Both the waveguide and the transistor have trenches with liners that can be separately optimized. The transistor has a salicide for source/drain contacts. During this process, a salicide block is used over the waveguide to prevent salicide formation in unwanted areas of the waveguide. The depth of the trench for the waveguide can be lower than that of the trench for the transistor isolation. Trench isolation depth can be set by an etch stop region that can be either a thin oxide layer or a buffer layer that is selectively etchable with respect to the top semiconductor layer and that can be used as a seed layer for growing the top semiconductor layer.

Claims (109)

1. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming optical liners on sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate;

forming trench liners on sidewalls within the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate, wherein forming the optical liners in the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate and forming the trench liners in the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate comprises one of: (i) simultaneously forming the optical liners and the trench liners, or (ii) independently forming the optical liners in the optical device portion from the trench liners in the electronic device portion;

filling the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate and the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate with a fill material;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate;

forming a salicide blocking layer overlying the optical device portion of the semiconductor substrate;

saliciding the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the active semiconductor layer within the optical device portion of the semiconductor substrate; and

forming an interlevel dielectric layer overlying the optical device portion and the electronic device portion of the semiconductor substrate, wherein the interlevel dielectric can act as an upper cladding layer of an optical device formed within the optical device portion of the semiconductor substrate.

2. The method of claim 1 , wherein forming the optical liners smoothes a roughness of the sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate.

3. The method of claim 1 , wherein forming the optical liners comprises an oxidation process optimized to provide a lowest loss waveguide as a function of a reduction in sidewall roughness.

4. The method of claim 1 , wherein the optical liners comprises a thickness greater than a thickness of the trench liner.

5. The method of claim 1 , wherein forming the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate comprises etching the openings, and wherein forming the trench liners comprises an oxidation process optimized to passivate the etched sidewalls, round corners of the openings, and to optimize a stress in the active semiconductor layer between the openings of the active semiconductor layer in the electronics device portion of the semiconductor substrate.

6. The method of claim 1 , wherein forming the trench liners comprises an oxidation process optimized to control stresses in the active semiconductor layer between the openings.

7. The method of claim 1 , wherein the trench liners have a thickness configured to provide an optimized high performance electronic device characteristic.

8. The method of claim 1 , wherein forming the salicide blocking layer comprises depositing TEOS on the optical device portion and the electronic device portion of the semiconductor substrate and then removing the TEOS from the electronic device portion.

9. The method of claim 1 , wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the optical device portion of the semiconductor substrate alone.

10. The method of claim 1 , wherein saliciding includes forming a salicidation metallization overlying the optical device portion and the electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the active semiconductor layer within the optical device portion of the semiconductor substrate.

11. The method of claim 10 , further wherein saliciding includes removing unreacted silicidation metallization.

12. The method of claim 1 , wherein forming openings within the active semiconductor layer in the first region and within the active semiconductor layer in the second region comprises one of: (i) simultaneously forming openings in the optical device portion and the electronic device portion, or (ii) independently forming openings in the optical device portion from openings in the electronic device portion, or (iii) using a dual trench process that includes forming the openings in the optical device portion to a first depth, and forming the openings in the electronic device portion to a second depth, the second depth being greater than the first depth.

13. The method of claim 12 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying a buried oxide.

14. The method of claim 13 , wherein the fill material includes one or more of TEOS, a furnace oxide, or a high density plasma oxide.

15. The method of claim 13 , wherein the fill material comprises a material selected to provide a desired optical index of refraction.

16. The method of claim 15 , further wherein the optical index of refraction of the fill material is less than an optical index of refraction of silicon.

17. The method of claim 13 , wherein the portion of the electronic device comprises at least a gate dielectric and a gate electrode on the active semiconductor layer.

18. The method of claim 17 , wherein the portion of the electronic device further comprises sidewall spacers adjacent sidewalls of the gate electrode.

19. The method of claim 18 , wherein the portion of the electronic device further comprises source/drain regions proximate the gate electrode, gate dielectric, and sidewall spacers within the electronic device portion of the semiconductor substrate.

20. The method of claim 1 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying a buried oxide.

21. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming openings within the active semiconductor layer in a first region of the semiconductor substrate and openings within the active semiconductor layer in a second region of the semiconductor substrate, wherein the first region corresponds to an optical device portion of the semiconductor substrate and the second region corresponds to an electronic device portion of the semiconductor substrate, wherein forming openings within the active semiconductor layer in the first region and within the active semiconductor layer in the second region comprises one of: (i) simultaneously forming openings in the optical device portion and the electronic device portion, or (ii) independently forming openings in the optical device portion from openings in the electronic device portion, or (iii) using a dual trench process that includes forming the openings in the optical device portion to a first depth, and forming the openings in the electronic device portion to a second depth, the second depth being greater than the first depth;

forming optical liners on sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate; and

22. The method of claim 21 , wherein forming the optical liners smoothes a roughness of the sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate.

23. The method of claim 21 , wherein forming the optical liners comprises an oxidation process optimized to provide a lowest loss waveguide as a function of a reduction in sidewall roughness.

24. The method of claim 21 , wherein the optical liners comprises a thickness greater than a thickness of the trench liner.

25. The method of claim 21 , wherein forming the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate comprises etching the openings, and wherein forming the trench liners comprises an oxidation process optimized to passivate the etched sidewalls, round corners of the openings, and to optimize a stress in the active semiconductor layer between the openings of the active semiconductor layer in the electronics device portion of the semiconductor substrate.

26. The method of claim 21 , wherein forming the trench liners comprises an oxidation process optimized to control stresses in the active semiconductor layer between the openings.

27. The method of claim 21 , wherein the trench liners comprises a thickness configured to provide an optimized high performance electronic device characteristic.

28. The method of claim 21 , wherein the optical portion of the semiconductor substrate can comprise one or more of an optical grating coupler, a waveguide, a wavelength selective filter, an optical modulator; or an arrayed waveguide grating.

29. The method of claim 21 , wherein forming openings comprises the dual trench process, and wherein forming the optical liner further includes forming the optical liners on the sidewalls, as well as on a bottom surface, of the openings within the active semiconductor layer in the first region.

30. The method of claim 21 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying a buried oxide.

31. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer, wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying an insulator, or (iv) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer overlying a bottom semiconductor layer, the second semiconductor layer being lattice matched to the bottom semiconductor layer, and the bottom semiconductor layer overlying an insulator;

forming optical liners on sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate; and

32. The method of claim 31 , wherein forming the optical liners smoothes a roughness of the sidewalls within the openings of the active semiconductor layer in the optical device portion of the semiconductor substrate.

33. The method of claim 31 , wherein forming the optical liners comprises an oxidation process optimized to provide a lowest loss waveguide as a function of a reduction in sidewall roughness.

34. The method of claim 31 , wherein the optical liners have a thickness greater than a thickness of the trench liner.

35. The method of claim 31 , wherein forming the openings of the active semiconductor layer in the electronic device portion of the semiconductor substrate comprises etching the openings, and wherein forming the trench liners comprises an oxidation process optimized to passivate the etched sidewalls, round corners of the openings, and to optimize a stress in the active semiconductor layer between the openings of the active semiconductor layer in the electronics device portion of the semiconductor substrate.

36. The method of claim 31 , wherein forming the trench liners comprises an oxidation process optimized to control stresses in the active semiconductor layer between the openings.

37. The method of claim 31 , wherein the trench liners have a thickness configured to provide an optimized high performance electronic device characteristic.

38. The method of claim 31 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a top silicon layer, the top silicon layer overlying a first buried oxide layer, the first buried oxide layer overlying an intermediate silicon layer, the intermediate silicon layer overlying a second bottom oxide layer, and the bottom oxide layer overlying a bottom handle wafer.

39. The method of claim 31 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a handle wafer and a donor wafer, the handle wafer having a silicon layer overlying a buried oxide layer overlying a bottom handle layer, and the donor wafer having a silicon layer and an oxide layer, further wherein the donor wafer is inverted and bonded to the silicon layer of the handle wafer via the oxide layer of the donor wafer.

40. The method of claim 31 , wherein the active semiconductor layer comprises the top, second, and bottom semiconductor layers, and further wherein the top semiconductor layer comprises silicon, the second semiconductor layer comprises SiGeC, and the bottom semiconductor layer comprises Si.

41. The method of claim 40 , further wherein respective concentrations of the Ge and C of the second semiconductor layer are selected so that the resulting SiGeC layer is lattice matched to the bottom semiconductor layer.

42. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate;

forming a salicide blocking layer overlying the optical device portion of the semiconductor substrate;

43. The method of claim 42 , wherein the optical portion of the semiconductor substrate can comprise one or more of an optical grating coupler, a waveguide, a wavelength selective filter, an optical modulator; or an arrayed waveguide grating.

44. The method of claim 42 , wherein forming openings comprises the dual trench process, and wherein forming the optical liners further includes forming the optical liner on the sidewalls, as well as on a bottom surface, of the openings within the active semiconductor layer in the first region.

45. The method of claim 42 , wherein forming the salicide blocking layer comprises depositing TEOS on the optical device portion and the electronic device portion of the semiconductor substrate and then removing the TEOS from the electronic device portion.

46. The method of claim 42 , wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the optical device portion of the semiconductor substrate alone.

47. The method of claim 42 , wherein saliciding includes forming a salicidation metallization overlying the optical device portion and the electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the active semiconductor layer within the optical device portion of the semiconductor substrate.

48. The method of claim 47 , further wherein saliciding includes removing unreacted silicidation metallization.

49. The method of claim 42 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying a buried oxide.

50. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate;

forming a salicide blocking layer overlying the optical device portion of the semiconductor substrate;

51. The method of claim 50 , wherein forming the salicide blocking layer comprises depositing TEOS on the optical device portion and the electronic device portion of the semiconductor substrate and then removing the TEOS from the electronic device portion.

52. The method of claim 50 , wherein forming the salicide blocking layer comprises patterning the blocking layer to overlie the optical device portion of the semiconductor substrate alone.

53. The method of claim 50 , wherein saliciding includes forming a salicidation metallization overlying the optical device portion and the electronic device portion of the semiconductor substrate, annealing the salicidation metallization to form salicided regions on exposed regions of semiconductor material within the electronic device portion of the semiconductor substrate, wherein the salicide blocking layer prevents salicidation of the salicidation metallization overlying the active semiconductor layer within the optical device portion of the semiconductor substrate.

54. The method of claim 53 , further wherein saliciding includes removing unreacted silicidation metallization.

55. The method of claim 50 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a top silicon layer, the top silicon layer overlying a first buried oxide layer, the first buried oxide layer overlying an intermediate silicon layer, the intermediate silicon layer overlying a second bottom oxide layer, and the bottom oxide layer overlying a bottom handle wafer.

56. The method of claim 50 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a handle wafer and a donor wafer, the handle wafer having a silicon layer overlying a buried oxide layer overlying a bottom handle layer, and the donor wafer having a silicon layer and an oxide layer, further wherein the donor wafer is inverted and bonded to the silicon layer of the handle wafer via the oxide layer of the donor wafer.

57. The method of claim 50 , wherein the active semiconductor layer comprises the top, second, and bottom semiconductor layers, and further wherein the top semiconductor layer comprises silicon, the second semiconductor layer comprises SiGeC, and the bottom semiconductor layer comprises Si.

58. The method of claim 57 , further wherein respective concentrations of the Ge and C of the second semiconductor layer are selected so that the resulting SiGeC layer is lattice matched to the bottom semiconductor layer.

59. A method for integrating an optical device and an electronic device on a semiconductor substrate, comprising:

providing a semiconductor substrate having an active semiconductor layer;

forming at least a portion of an electronic device on the active semiconductor layer within the electronic device portion of the semiconductor substrate; and

60. The method of claim 59 , wherein the optical portion of the semiconductor substrate can comprise one or more of an optical grating coupler, a waveguide, a wavelength selective filter, an optical modulator; or an arrayed waveguide grating.

61. The method of claim 59 , wherein forming openings comprises the dual trench process, and wherein forming the optical liners further includes forming the optical liner on the sidewalls, as well as on a bottom surface, of the openings within the active semiconductor layer in the first region.

62. The method of claim 59 , wherein the active semiconductor layer comprises one of: (i) a top semiconductor layer of a semiconductor-on-insulator substrate, or (ii) a top semiconductor layer of a dual semiconductor-on-insulator substrate, or (iii) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer having an etch selectivity different from an etch selectivity of the top semiconductor layer, and the second semiconductor layer overlying a bottom semiconductor layer, the bottom semiconductor layer overlying an insulator, or (iv) a top semiconductor layer overlying a second semiconductor layer, the second semiconductor layer overlying a bottom semiconductor layer, the second semiconductor layer being lattice matched to the bottom semiconductor layer, and the bottom semiconductor layer overlying an insulator.

63. The method of claim 62 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a top silicon layer, the top silicon layer overlying a first buried oxide layer, the first buried oxide layer overlying an intermediate silicon layer, the intermediate silicon layer overlying a second bottom oxide layer, and the bottom oxide layer overlying a bottom handle wafer.

64. The method of claim 62 , wherein the semiconductor substrate comprises the dual semiconductor-on-insulator substrate, and wherein the dual semiconductor-on-insulator substrate comprises a handle wafer and a donor wafer, the handle wafer having a silicon layer overlying a buried oxide layer overlying a bottom handle layer, and the donor wafer having a silicon layer and an oxide layer, further wherein the donor wafer is inverted and bonded to the silicon layer of the handle wafer via the oxide layer of the donor wafer.

65. The method of claim 62 , wherein the active semiconductor layer comprises the top, second, and bottom semiconductor layers, and further wherein the top semiconductor layer comprises silicon, the second semiconductor layer comprises SiGeC, and the bottom semiconductor layer comprises Si.

66. The method of claim 62 , further wherein respective concentrations of the Ge and C of the second semiconductor layer are selected so that the resulting SiGeC layer is lattice matched to the bottom semiconductor layer.

67. The method of claim 62 , wherein the active semiconductor layer comprises the top, second, and bottom semiconductor layers, and further wherein forming the openings in the first region comprises forming the openings in the first region through the top semiconductor layer of the active semiconductor layer alone, and still further wherein forming the openings in the second region comprises forming the openings in the second region through the top semiconductor layer, the second semiconductor layer and the bottom semiconductor layer of the active semiconductor layer.

Assignments (19)

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.

Reel/Frame 052917/0001 →

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

Reel/Frame 052915/0001 →

CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019

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From: MORGAN STANLEY SENIOR FUNDING, INC.

To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.

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CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017

From: CITIBANK, N.A.

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CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017

From: FREESCALE SEMICONDUCTOR INC.

To: NXP USA, INC.

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CHANGE OF NAME Recorded Nov 8, 2016

From: FREESCALE SEMICONDUCTOR INC.

To: NXP USA, INC.

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RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

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RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016