IP Library Granted Patent US 6,916,682
Granted Patent B2
US 6,916,682 · App. 10/008,800 · Granted Jul 12, 2005

Semiconductor package device for use with multiple integrated circuits in a stacked configuration and method of formation and testing

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Quick Facts
Patent No.
US 6,916,682
App. No.
10/008,800
Granted
Jul 12, 2005
Kind
B2
Abstract

A package device ( 10, 100 ) has one integrated circuit ( 22, 122 ) in a cavity ( 20, 120 ) in a package substrate ( 12, 122 ) and electrically coupled to one side ( 50, 150 ) of the package substrate. A second integrated circuit ( 32, 132 ) is mounted on another side of the package device and electrically coupled to that side as well. A third integrated circuit ( 38, 138 ) or more may be mounted on the second integrated circuit. Pads ( 16, 116, 116 ) useful for testing are present on both sides of the package substrate. The integrated circuits may be tested before final encapsulation to reduce the risk of providing completed packages with non-functional integrated circuits therein.

Claims (60)

1. A method of forming a package device, comprising;

providing a package substrate having a first side and a second side and having first pads on the first side and second pads on the second side;

placing a first integrated circuit on the first side and a second integrated circuit on a second side, wherein die attach material is interposed between the first integrated circuit and the second integrated circuit;

electrically connecting the first integrated circuit to the first pads and the second integrated circuit to the second pads; and

testing the first integrated circuit and the second integrated circuit by applying test probes to the first pads and the second pads,

wherein at least one of the first pads is electrically independent of all of the second pads, and wherein encapsulating material does not overlie at least one pad.

2. The method of claim 1 , wherein the step of attaching is further characterized by:

the first integrated circuit being placed on the first side prior to the second integrated circuit being placed on the second side.

3. The method of claim 2 , wherein the step of electrically connecting is further characterized by:

the first integrated circuit being electrically connected to the first pads prior to the second integrated circuit being electrically connected to the second pads.

4. A method for forming a package device, comprising:

providing a package substrate having a first surface along a first plane and second surface along a second plane, wherein the package substrate has a cavity between the first plane and the second plane, and wherein the package substrate has first pads on the first surface and has second pads on the second surface;

placing a first integrated circuit in the cavity;

placing a second integrated circuit adjacent to the first integrated circuit outside the cavity, such that die attach material is interposed between the first integrated circuit and the second integrated circuit;

depositing encapsulating material over the first integrated circuit and the second integrated circuit;

electrically connecting the first integrated circuit to the first pads and the second integrated circuit to the second pads; and

testing the first integrated circuit and the second integrated circuit by applying test probes to the first pads and the second pads,

wherein at least one of the first pads is electrically independent of all of the second pads, and wherein the encapsulating material does not overlie at least one pad.

5. The method of claim 4 , wherein the step of depositing comprises:

depositing a first portion of the encapsulating material over the first integrated circuit prior to the step of placing the second integrated circuit; and

depositing a second portion of the encapsulating material over the second integrated circuit.

6. The method of claim 5 , further comprising:

placing a third integrated circuit adjacent to the second integrated circuit prior to the step of depositing the second portion of encapsulating material.

7. The method of claim 6 , wherein the third integrated circuit is stacked at least partially overlying at least one of the first and second integrated circuits.

8. The method of claim 5 , wherein the step of depositing the first portion of the encapsulating material comprises transfer molding the encapsulating material, and wherein the step of depositing a second portion of the encapsulating material comprises transfer molding the encapsulating material.

9. The method of claim 4 , wherein the package substrate further comprises first bond fingers on the first surface, and second bond fingers on the second surface.

10. The method of claim 9 , wherein the step of electrically connecting the first integrated circuit comprises wire bonding.

11. The method of claim 4 , wherein the package substrate further comprises a supporting member along the second plane of the substrate.

12. The method of claim 11 , wherein the supporting member is between the first integrated circuit and the second integrated circuit.

13. The method of claim 12 , wherein the supporting member is electrically conductive.

14. The method of claim 11 , further comprising removing the supporting member prior to step of placing the second integrated circuit.

15. The method of claim 14 , wherein supporting member is tape.

16. A method for forming a package device, comprising:

providing a package substrate having a first surface along a first plane and second surface along a second plane, wherein the package substrate has a cavity between the first plane and the second plane;

placing a first integrated circuit in the cavity;

placing a second integrated circuit adjacent to the first integrated circuit outside the cavity, such that a supporting member is interposed between the first integrated circuit and the second integrated circuit; and

depositing encapsulating material over the first integrated circuit and the second integrated circuit,

wherein the package substrate is not formed from encapsulating material, and wherein the step of depositing comprises:

depositing a first portion of the encapsulating material over the first integrated circuit prior to the step of placing the second integrated circuit; and

depositing a second portion of the encapsulating material over the second integrated circuit,

wherein the method further comprises placing a third integrated circuit adjacent to the second integrated circuit prior to the step of depositing the second portion of encapsulating material

wherein the method further comprises

electrically connecting the first integrated circuit to first pads, wherein the first pads are located on the first surface;

electrically connecting the second integrated circuit to second pads, wherein the second pads are located on the second surface; and

testing the first integrated circuit and the second integrated circuit by applying test probes to the first pads and the second pads.

17. A method for forming a package device, comprising:

providing a package substrate having a first side and a second side;

providing first pads on the first side;

providing second pads on the second side;

providing a first integrated circuit mounted to the package substrate;

providing a second integrated circuit mounted to the package substrate; and

providing a third integrated circuit adjacent to the second integrated circuit,

wherein the first integrated circuit is electrically connected to the first pads and the second integrated circuit is electrically connected to the second pads.

wherein the first pads and the second pads are further characterized as being useful for receiving test probes for testing, and

wherein one of the first and second pads is not covered by an encapsulating material and is exposed for receiving one of the test probes.

18. The method of claim 17 , wherein the substrate is further characterized as having a cavity and the first integrated circuit is further characterized as being in the cavity.

19. The method of claim 18 , wherein the second integrated circuit is mounted to the substrate by adhesive die attach tape.

20. The method of claim 19 , wherein the first integrated circuit is adjacent to the second integrated circuit.

21. The method of claim 20 , further comprising providing a supporting member between the first integrated circuit and the second integrated circuit.

22. The method of claim 21 , wherein the supporting member comprises die attach material.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2001
From: GERBER, MARK A.; O'CONNOR, SHAWN M.; THOMPSON, TRENT A.
To: MOTOROLA, INC.
Reel/Frame 012377/0251 →