Processes for forming electronic devices including non-volatile memory
View Patent ↗A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.
1. A process for forming a non-volatile memory device, wherein the process comprises:
forming a trench field isolation region over a substrate to define an active region in the substrate, wherein the active region comprises a first portion, a non-volatile memory portion, and a logic portion;
forming a sacrificial insulating layer over the first portion of the active region, the non-volatile memory portion of the active region, and the logic portion of the active region;
removing a first portion of the sacrificial insulating layer from over the non-volatile memory portion of the active region, wherein a first portion of the trench field isolation region from over the non-volatile memory portion is exposed after the first portion of the sacrificial insulating layer is removed;
forming a first gate dielectric layer over the non-volatile memory portion of the active region;
forming a charge storage layer over the substrate;
forming a control gate conductor layer over the charge storage layer;
removing first portions of the charge storage layer and control gate conductor layer that overlie the first portion of the active region;
removing a second portion of the sacrificial insulating layer from over the first portion of the active region, wherein a second portion of the trench field isolation region is exposed after the second portion of the sacrificial insulating layer is removed;
forming a second gate dielectric layer over the first portion of the active region, wherein forming the second gate dielectric layer is performed after forming the first gate dielectric layer;
forming a first resist mask over a first part of the logic portion of the active region to define a first opening;
removing second portions of the control gate conductor layer and charge storage layer underlying the first opening in the first resist mask;
implanting a first dopant for a first well region within the first part of the logic portion, wherein the first well region underlies the first opening;
removing a third portion of the sacrificial insulating layer from over the first part of the logic portion of the active region, wherein a third portion of the trench field isolation region is exposed after the third portion of the sacrificial insulating layer is removed;
removing the first resist mask; and
forming a third gate dielectric layer over the logic portion of the active region, wherein forming the third gate dielectric layer is performed after forming the first gate dielectric layer, forming the second gate dielectric layer, and implanting the first dopant.
2. The process of claim 1 , wherein forming the trench field isolation region is performed such that the active region further comprises an I/O portion, and wherein the process further comprises:
removing a fourth portion of the sacrificial insulating layer from over the I/O portion of the active region, wherein a fourth portion of the trench field isolation region is exposed after the fourth portion of the sacrificial insulating layer is removed; and
forming a fourth gate dielectric layer over the active region,
wherein the fourth gate dielectric layer is part of I/O components within the non-volatile memory device, and the second gate dielectric layer is part of HV components within the non-volatile memory device.
3. The process of claim 2 , wherein forming the second gate dielectric layer and forming the fourth gate dielectric layer are formed such that the second and fourth gate dielectric layers have substantially a same thickness.
4. The process of claim 2 , wherein forming the second gate dielectric layer and forming the fourth gate dielectric layer are performed substantially simultaneously.
5. The process of claim 4 , wherein removing the second portion of the sacrificial insulating layer and removing the fourth portion of the sacrificial insulating layer are performed substantially simultaneously.
6. The process of claim 2 , wherein:
forming the first gate dielectric layer comprises forming the first gate dielectric layer within non-volatile memory cells;
forming the second gate dielectric layer comprises forming the second gate dielectric layer within HV components;
forming the third gate dielectric layer comprises forming the third gate dielectric layer within logic components.
7. The process of claim 1 , wherein:
removing the first portion of the sacrificial insulating layer removes the sacrificial insulating layer only from over the non-volatile memory portion of the active region; removing the second portion of the sacrificial insulating layer removes the sacrificial insulating layer only from over the first portion of the active region; and removing the third portion of the sacrificial insulating layer removes the sacrificial insulating layer only from over the first part of the logic portion of the active region.
8. The process of claim 1 , wherein forming the third gate dielectric layer is performed after forming the first gate dielectric layer and forming the second gate dielectric layer.
9. The process of claim 8 , wherein forming the first gate dielectric layer is performed before forming the second gate dielectric layer.
10. The process of claim 1 , further comprising forming a first gate conductor layer over the substrate including the first portion of the active region.
11. The process of claim 1 , further comprising:
forming a second resist mask over a second part of the logic portion of the active region to define a second opening;
removing third portions of the control gate conductor layer and charge storage layer underlying the second opening in the second resist mask;
implanting a second dopant for a second well region within the logic portion, wherein the second well region underlies the second opening, and the second dopant has a conductivity type opposite the first dopant; and
removing the second resist mask,
wherein:
implanting the second dopant is performed before forming the third gate dielectric layer; and
removing the third portion of the sacrificial insulating layer further comprises removing a second part of the sacrificial insulating layer that overlies the second part of the logic portion.
12. The process of claim 1 , wherein at least a portion of the second gate dielectric layer is formed using steam.
13. The process of claim 1 , wherein:
the first portion of the trench field isolation region lies immediately adjacent to the first portion of the active region, the second portion of the trench field isolation region lies immediately adjacent to the non-volatile memory portion of the active region, and the third portion of the trench field isolation region lies immediately adjacent to the logic portion of the active region;
the first portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the second gate dielectric layer;
the second portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the first gate dielectric layer; and
the third portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the third gate dielectric layer.
14. The process of claim 1 , wherein forming the first gate dielectric layer, forming the second gate dielectric layer, and forming the third gate dielectric layer are formed such that the first, second, and third gate dielectric layers have different thicknesses as compared to one another.
15. The process of claim 1 , wherein:
forming the first gate dielectric layer comprises forming the first gate dielectric layer within non-volatile memory cells;
forming the second gate dielectric layer comprises forming the second gate dielectric layer within I/O components; and
forming the third gate dielectric layer comprises forming the third gate dielectric layer within logic components
16. The process of claim 1 , wherein:
forming the first gate dielectric layer comprises forming the first gate dielectric layer within non-volatile memory cells;
forming the second gate dielectric layer comprises forming the second gate dielectric layer within HV components; and
forming the third gate dielectric layer comprises forming the third gate dielectric layer within logic components.
17. The process of claim 1 , wherein forming the third gate dielectric layer and forming the second gate dielectric layer are performed after forming the first gate dielectric layer.
18. The process of claim 1 , wherein removing the second portion of the sacrificial insulating layer, forming the second gate dielectric layer, removing the third portion of the sacrificial insulating layer, and forming the third gate dielectric layer are performed after forming the control gate conductor layer.
19. The process of claim 1 , further comprising forming a second well region within the first portion of the active region.
20. A process for forming a non-volatile memory device, wherein the process comprises:
forming a trench field isolation region over a substrate to define an active region in the substrate, wherein:
the active region comprises a first portion, a non-volatile memory portion, and a logic portion;
the trench field isolation region comprises a first portion, a second portion, and a third portion;
the first portion of the trench field isolation region lies immediately adjacent to the first portion of the active region;
the second portion of the trench field isolation region lies immediately adjacent to the non-volatile memory portion of the active region; and
the third portion of the trench field isolation region lies immediately adjacent to the logic portion of the active region;
forming a sacrificial insulating layer over the first portion of the active region, the non-volatile memory portion of the active region, and the logic portion of the active region;
removing a first portion of the sacrificial insulating layer from over the non-volatile memory portion of the active region, wherein the first portion of the trench field isolation region from over the non-volatile memory portion is exposed after the first portion of the sacrificial insulating layer is removed;
forming a first gate dielectric layer over the non-volatile memory portion of the active region;
forming a charge storage layer over the substrate;
forming a control gate conductor layer over the charge storage layer;
removing portions of the charge storage layer and control gate conductor layer that overlie the first portion of the active region and the logic portion of the active region;
removing a second portion of the sacrificial insulating layer from over the first portion of the active region, wherein a second portion of the trench field isolation region is exposed after the second portion of the sacrificial insulating layer is removed;
forming a second gate dielectric layer over the first portion of the active region, wherein forming the second gate dielectric layer is performed after forming the first gate dielectric layer;
removing a third portion of the sacrificial insulating layer from over the logic portion of the active region, wherein a third portion of the trench field isolation region is exposed after the third portion of the sacrificial insulating layer is removed; and
forming a third gate dielectric layer over the logic portion of the active region, wherein forming the third gate dielectric layer is performed after forming the first gate dielectric layer and forming the second gate dielectric layer,
wherein:
the first portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the second gate dielectric layer;
the second portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the first gate dielectric layer; and
the third portion of the field isolation region is exposed to a single oxide etch between forming the sacrificial insulating layer and forming the third gate dielectric layer.