IP Library Granted Patent US 7,034,558
Granted Patent B2
US 7,034,558 · App. 10/209,745 · Granted Apr 25, 2006

Test system for device and method thereof

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Quick Facts
Patent No.
US 7,034,558
App. No.
10/209,745
Granted
Apr 25, 2006
Kind
B2
Abstract

In one embodiment, a contactor ( 200 ) is provided. The contactor ( 200 ) comprises a device side ( 210 ), a test circuit board side ( 155 ), and a thickness ( 110 ). The device side ( 210 ) is in communication with at least three electrical contact points ( 140, 141, 142 ) of the device ( 170 ). The test circuit board side ( 155 ) includes a fourth electrical contact point ( 193 ) in electrical communication with the circuit board ( 150 ). The contactor ( 200 ) also includes a first electrical pathway ( 220 ) between the first electrical contact point ( 140 ) and the second electrical contact point ( 142 ). The first electrical pathway ( 220 ) bypasses the circuit board ( 150 ). The contactor ( 200 ) further includes a second electrical pathway ( 270 ) between the third electrical contact point ( 142 ) and the fourth electrical contact point ( 193 ).

Claims (77)

1. A system for electrically connecting a device under test and a test circuit board, the device comprising at least a first electrical contact point, a second electrical contact point, and a third electrical contact point, the system comprising:

a contactor for electrically connecting the device under test to the test circuit board,

the contactor including:

means for electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point; and

means for bringing the third electrical contact point in electrical communication with the test circuit board;

wherein the contactor includes a device side and a circuit board side:

wherein the device side faces the device under test and the circuit board side faces the test circuit board during a test of the device under test;

wherein the contactor further includes dielectric material located between the circuit board side and the device side, the dielectric material including a portion located between the means for electrically bypassing the test circuit board and the means for bringing the third electrical contact point in electrical communication with the test circuit board.

2. The system of claim 1 , wherein the means for electrically bypassing further comprises means for shorting the first electrical contact point to the second electrical contact point.

3. A system for electrically connecting a device under test and a test circuit board, the device comprising at least a first electrical contact point, a second electrical contact point, and a third electrical contact point, the system comprising:

a contactor for electrically connecting the device under test to the test circuit board,

the contactor including;

means for electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point; and

means for bringing the third electrical contact point in electrical communication with the test circuit board;

wherein the means for electrically bypassing comprises a slug.

4. A system for electrically connecting a device under test and a test circuit board, the device comprising at least a first electrical contact point, a second electrical contact point, and a third electrical contact point, the system comprising:

a contactor for electrically connecting the device under test to the test circuit board,

the contactor including:

means for electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point; and

means for bringing the third electrical contact point in electrical communication with the test circuit board;

wherein the means for electrically bypassing comprises a flexible circuit.

5. A system for electrically connecting a device under test and a test circuit board, the device comprising at least a first electrical contact point, a second electrical contact point, and a third electrical contact point, the system comprising:

means for electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point; and

means for bringing the third electrical contact point in electrical communication with the test circuit board;

wherein means for bypassing comprise a means for shorting an emitter pin of an amplifier to ground.

6. A method for testing an electronic device, the method comprising:

electrically connecting the device to a test circuit board using a contactor, the contactor includes a circuit board side and the test circuit board includes a side, the device having at least a first electrical contact point, a second electrical contact point, and a third electrical contact point;

electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point using a first electrical pathway of the contactor;

bringing the third electrical contact point in communication with the test circuit board using a second electrical pathway of the contactor; and applying a test method to the device;

wherein the electrically connecting the device to a test circuit board further includes having the contactor positioned such that the circuit board side faces the side of the test circuit board;

wherein the contactor includes a device side;

wherein the contactor includes dielectric material located between the circuit board side and the device side, the dielectric material including a portion located between the first electrical pathway and the second electrical pathway.

7. The method of claim 6 wherein:

the contactor includes a fourth electrical contact point electrically connected to the second electrical pathway;

the test circuit board includes an electrical contact point;

wherein the bringing the third electrical contact point in communication with the test circuit board includes the fourth electrical contact point electrically contacting the electrical contact point of the test circuit board.

8. The method of claim 6 wherein the contactor includes a device side wherein the electrically connecting the device to a test circuit board further includes having the contactor positioned such that the device side faces the device under test.

9. A method for testing an electronic device, the method comprising:

electrically connecting the device to a test circuit board, the device having at least a first electrical contact point, a second electrical contact point, and a third electrical contact point;

electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point;

bringing the third electrical contact point in communication with the test circuit board; and

applying a test method to the device;

wherein the device comprises an amplifier; wherein the applying a test method comprises applying a gain test.

10. A method for testing an electronic device, the method comprising:

electrically connecting the device to a test circuit board, the device having at least a first electrical contact point, a second electrical contact point, and a third electrical contact point;

electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point;

bringing the third electrical contact point in communication with the test circuit board; and

applying a test method to the device; wherein the device comprises an amplifier; wherein the applying a test method comprises applying third order intercept test.

11. A method for testing an electronic device, the method comprising:

electrically connecting the device to a test circuit board, the device having at least a first electrical contact point, a second electrical contact point, and a third electrical contact point;

electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point;

bringing the third electrical contact point in communication with the test circuit board; and

applying a test method to the device; wherein the device comprises an amplifier; wherein the applying a test method comprises applying noise figure test.

12. A method for testing an electronic device, the method comprising:

electrically connecting the device to a test circuit board, the device having at least a first electrical contact point, a second electrical contact point, and a third electrical contact point;

electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point;

bringing the third electrical contact point in communication with the test circuit board; and

applying a test method to the device;

wherein the device comprises an amplifier;

wherein the electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point further comprises shorting the emitter pin of the amplifier to ground.

13. A method of reducing the inductance between an amplifier under test and a test circuit board, the method comprising:

temporarily bringing the amplifier in electrical communication with the test circuit board;

electrically bypassing the test circuit board between an emitter pin of the amplifier and a second pin of the amplifier; and

grounding the second pin.

14. A system for electrically connecting a device under test and a test circuit board, the device comprising at least a first electrical contact point, a second electrical contact point, and a third electrical contact point, the system comprising:

a contactor for electrically connecting the device under test to the test circuit board,

the contactor including:

means for electrically bypassing the test circuit board between the first electrical contact point and the second electrical contact point; and

means for bringing the third electrical contact point in electrical communication with the test circuit board;

wherein the contactor further includes:

a device side;

a circuit board side;

wherein the device side comprises at least three electrical contact points to provide electrical contact with the first electrical contact point, the second electrical contact point, and the third electrical contact point of the device under test;

wherein the circuit board side comprises a fourth electrical contact point to provide electrical contact with the circuit board;

wherein the means for electrically bypassing the test circuit board includes a first electrical pathway between a first electrical contact point of the device side and a second electrical contact point of the device side, wherein the first electrical pathway bypasses the circuit board;

wherein the means for bringing the third electrical contact point includes a second electrical pathway between a third electrical contact point of the device side and the fourth electrical contact point of the circuit board side;

wherein the contactor further includes dielectric material located between the circuit board side and the device side, the dielectric material including a portion located between the first electrical pathway and the second electrical pathway.

Assignments (17)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →