Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integration
View Patent ↗A method for making a semiconductor device is disclosed. In accordance with the method, a semiconductor structure is provided which includes (a) a substrate ( 203 ), (b) first and second gate electrodes ( 219 ) disposed over the substrate, each of the first and second gate electrodes having first and second sidewalls, and (c) first ( 223 ) and second ( 225 ) sets of spacer structures disposed adjacent to the first and second gate electrodes, respectively. A first layer of photoresist ( 231 ) is then disposed over the structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered, after which the first set of spacer structures is partially etched.
1. A method for making a semiconductor device, comprising:
providing a semiconductor structure comprising (a) a substrate, (b) first and second gate electrodes disposed over the substrate, and (c) first and second sets of spacer structures disposed adjacent to said first and second gate electrodes, respectively, wherein each of said first and second sets of spacer structures comprises a first and second spacer disposed on opposing sides of one of said first and second gate electrodes, wherein said a topmost surface of said first set of spacer structures is coplanar with said first gate electrode, and wherein a topmost surface of said second set of spacer structures is coplanar with said second gate electrode;
disposing a first layer of photoresist over the semiconductor structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered;
partially etching the first set of spacer structures;
disposing a second layer of photoresist over the semiconductor structure such that the second set of spacer structures is exposed and the first set of spacer structures is covered; and
partially etching the second set of spacer structures.
2. The method of claim 1 , wherein the first and second sets of spacer structures are etched such that they have substantially different dimensions.
3. The method of claim 1 , wherein the semiconductor structure further comprises a third gate electrode disposed over the substrate and having a third set of spacer structures disposed adjacent thereto, and wherein the first and second layers of photoresist also cover the third set of spacer structures.
4. The method of claim 3 , further comprising:
disposing a third layer of photoresist over the semiconductor structure such that the third set of spacer structures is exposed and the first and second sets of spacer structures are covered; and
partially etching the third set of spacer structures.
5. The method of claim 4 , wherein the first, second and third sets of spacer structures are etched such that they have substantially different dimensions.
6. The method of claim 5 , wherein at least two of the first, second and third sets of spacer structures are subjected to a recess etch.
7. The method of claim 1 , wherein the first and second sets of spacer structures are etched with first and second distinct etches.
8. The method of claim 1 , wherein the first and second sets of spacer structures are etched with first and second distinct etchants.
9. The method of claim 1 , wherein the first and second sets of spacer structures are etched for first and second distinct durations.
10. The method of claim 1 , wherein the first and second sets of spacer structures are subjected to a recess etch, and wherein the first and second gate electrodes are subjected to silicidation.
11. The method of claim 1 , wherein each of said first and second gate electrodes has first and second sidewalls, and wherein said first and second sets of spacer structures are disposed adjacent to said sidewalls.
12. The method of claim 11 , wherein said first and second sets of spacer structures are disposed adjacent to said first and second sidewalls, and are separated therefrom by a layer of gate oxide.
13. The method of claim 12 , wherein the etch used to partially etch the first set of spacer structures does not remove the layer of gate oxide.
14. The method of claim 1 , further comprising the step of forming a deep implant region in the substrate after the first and second sets of spacer structures are etched.
15. A method for making a semiconductor device, comprising:
providing a semiconductor structure comprising (a) a substrate, (b) first, second and third gate electrodes disposed over the substrate, and (c) first, second and third sets of spacer structures disposed adjacent to said first, second and third gate electrodes, respectively, wherein each of said first, second and third sets of spacer structures comprises a first and second spacer disposed on opposing sides of one of said first, second and third gate electrodes wherein said a topmost surface of said first set of spacer structures is coplanar with said first gate electrode, and wherein a topmost surface of said second set of spacer structures is coplanar with said second gate electrode;
disposing a first layer of photoresist over the semiconductor structure such that the first set of spacer structures is exposed and the second set of spacer structures is covered;
partially etching the first set of spacer structures;
disposing a second layer of photoresist over the semiconductor structure such that the second set of spacer structures is exposed and the first set of spacer structures is covered; and
partially etching the second set of spacer structures.
16. The method of claim 15 , further comprising the steps of:
disposing a third layer of photoresist over the semiconductor structure such that the third set of spacer structures is exposed and the first and second sets of spacer structures are covered; and
partially etching the third set of spacer structures.
17. The method of claim 16 , further comprising the step of forming deep implant regions in the substrate adjacent to each of said first, second and third sets of spacer structures.
18. The method of claim 15 , wherein each of the first, second and third sets of spacer structures have different dimensions.