Method and apparatus for doherty amplifier biasing
View Patent ↗Apparatus and methods are described for biasing amplifiers with multiple outputs. A semiconductor die may include a reference Field Effect Transistor (FET) integrated on the semiconductor die and coupled to an amplifier integrated on the semiconductor die. A voltage offset circuit may also be integrated on the semiconductor die for determining the voltage needed to operate the amplifier.
1. An amplifier circuit, comprising:
a semiconductor die;
a Doherty amplifier integrated on the semiconductor die, the Doherty amplifier including a peaking amplifier and a carrier amplifier coupled to the peaking amplifier;
a resistor divider network integrated on the semiconductor die and coupled to the carrier amplifier, the resistor divider network biasing the peaking amplifier; and
a self-bias Field Effect Transistor which automatically tracks variations in device parameters of the peaking amplifier integrated on the semiconductor die and coupled to the Doherty amplifier,
the self-bias Field Effect Transistor and resistor divider network together biasing the Doherty amplifier.
2. An amplifier circuit, comprising:
a semiconductor die;
a first and second amplifiers integrated on the semiconductor die;
a resistor divider network integrated on the semiconductor for biasing the first amplifier; and
a self-bias Field Effect Transistor which automatically tracks variations in device parameters of the first amplifier integrated on the semiconductor die and coupled to the second amplifier;
the self-bias Field Effect Transistor and resistor divider network together biasing the second amplifier.
3. The amplifier circuit of claim 2 , the first amplifier comprising a peaking amplifier.
4. The amplifier circuit of claim 3 , the second amplifier comprising a carrier amplifier coupled to the peaking amplifier.
5. The amplifier circuit of claim 4 , the peaking amplifier being coupled to the carrier amplifier via the resistor divider network.
6. The amplifier circuit of claim 4 , the self-bias Field Effect Transistor being coupled to the carrier amplifier.
7. A method, comprising:
providing a semiconductor die having an amplifier integrated on the semiconductor die, a self-bias Field Effect Transistor integrated on the semiconductor die, and a resistor divider network integrated on the semiconductor die;
operating the self-bias Field Effect Transistor to track device parameters of the amplifier; and
operating the self-bias Field Effect Transistor and the resistor divider network to bias the amplifier based on tracked changes to the device parameters of the amplifier.
8. The method of claim 7 , the amplifier comprising a peak amplifier.
9. The method of claim 7 , the amplifier comprising a carrier amplifier.
10. The method of claim 7 , the step of tracking device parameters comprising tracking a threshold voltage and transconductance of the amplifier.
11. A method, comprising:
providing a semiconductor die comprising
a first and second amplifier integrated on the semiconductor die;
a self-bias Field Effect Transistor which automatically tracks variations in device parameters of the first amplifier integrated on the semiconductor die, and
a the resistor divider network integrated on the semiconductor die;
operating the self-bias Field Effect Transistor to provide a reference voltage to the second amplifier; and
operating the resistor divider network bias the first amplifier proportional to the reference voltage of the second amplifier.
12. The method of claim 11 , the first amplifier comprising a peaking amplifier and the second amplifier comprising a carrier amplifier.
13. The method of claim 1 , the self-bias Field Effect Transistor being coupled to a gate terminal of the carrier amplifier.
14. The method of claim 1 , the self-bias Field Effect Transistor tracking device parameters of the peaking amplifier.