Semiconductor process for forming stress absorbent shallow trench isolation structures
View Patent ↗A semiconductor fabrication process includes patterning a hard mask over a semiconductor substrate to expose an isolation region and forming a trench in the isolation region. A flowable dielectric is deposited in the trench to partially fill the trench and a capping dielectric is deposited overlying the first oxide to fill the trench. The substrate may be a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer and the trench may extend partially into the BOX layer. The flowable dielectric may be a spin deposited flowable oxide or a CVD BPSG oxide. The flowable dielectric isolation structure provides a buffer that prevents stress induced on one side of the isolation structure from creating stress on the other side of the structure. Thus, for example, compressive stress created by forming silicon germanium on silicon in PMOS regions does not create compressive stress in NMOS regions.
1. A semiconductor fabrication process, comprising:
patterning a photoresist layer over a semiconductor substrate to expose an isolation region of the substrate, wherein the substrate is a silicon on insulator (SOI) substrate including a buried oxide (BOX) layer overlying a substrate bulk and an active semiconductor active layer overlying the BOX layer;
forming a trench in the isolation region;
forming a first dielectric in the trench to partially fill the trench wherein the first dielectric is a flowable dielectric;
depositing a capping dielectric overlying the first dielectric to create a trench isolation structure;
forming a material adjacent a first sidewall of the trench to create stress in the substrate adjacent the first sidewall, wherein the trench isolation structure prevents the stress adjacent the first sidewall from causing stress adjacent a second sidewall of the trench; and
prior to patterning the photoresist layer, forming a hard mask layer overlying the substrate, wherein the hard mask comprises silicon nitride.
2. The method of claim 1 , wherein forming the trench comprises forming trench extending through the active layer and partially into the BOX layer.
3. The method of claim 1 , wherein forming the first dielectric includes spin depositing a flowable oxide.
4. The method of claim 1 , wherein forming the first dielectric includes depositing a BPSG oxide.
5. The method of claim 1 , further comprising, prior to forming the first dielectric, forming an oxide liner adjacent the sidewalls of the isolation trench and a silicon nitride liner adjacent the oxide liner.
6. The method of claim 1 , wherein forming the capping dielectric comprises depositing a high density plasma oxide overlying the first dielectric.
7. A semiconductor fabrication process, comprising:
forming a narrow isolation trench in a wafer substrate, wherein a narrow isolation trench has a lateral dimension of less than approximately1 micrometer, wherein the wafer is a silicon on insulator (SOI) wafer, wherein the SQl wafer includes a buried oxide overlying a substrate bulk and a semiconductive active layer overlying the BOX layer and further wherein forming the narrow isolation trench comprises forming a narrow isolation trench extending through the active layer and partially into the BOX layer,
partially filling the narrow isolation trench with a first dielectric, the first dielectric having a flow temperature no greater than approximately 900 C.; and
forming a capping dielectric overlying the first dielectric using a high density plasma deposition process to fill the narrow isolation trench.
8. The method of claim 7 , wherein partially filling the narrow isolation trench with a first dielectric comprises partially filling the narrow isolation trench with a spin-on flowable oxide.
9. The method of claim 7 , wherein partially filling the narrow isolation trench with a first dielectric comprises partially filling the narrow isolation trench with borophosphosilicate glass (BPSG).
10. The method of claim 7 , wherein partially filling the narrow isolation trench with the first dielectric comprises depositing a TEOS film and implanting the TEOS film with at least one species selected from the group consisting of boron and phosphorous.
11. The method of claim 7 , wherein forming the capping dielectric comprises forming the capping dielectric using a plasma having a plasma density in excess of approximately 10 10 ions/cm 3 .
12. The method of claim 7 , further comprising, while forming the narrow isolation trench, forming a wide isolation trench having a lateral dimension of greater than 1 micrometer and, prior to depositing the first dielectric in the narrow isolation trench:
depositing an isolation dielectric in the narrow and wide isolation trench;
patterning a mask overlying the wafer to expose the narrow isolation trench; and
removing the isolation dielectric from the narrow isolation trench.
13. An isolation structure suitable for use in an integrated circuit, comprising:
a flowable dielectric partially filling an isolation trench formed in a semiconductor substrate, wherein the semiconductor substrate comprises a semiconductor active layer overlying a buried oxide (BOX) layer overlying a substrate bulk, and wherein the isolation trench extends through the active semiconductor layer and partially into the BOX layer; and
a capping dielectric overlying the flowable dielectric.
14. The isolation structure of claim 13 , wherein the semiconductor substrate adjacent a first side of the isolation trench exhibits compressive stress and wherein the substrate adjacent a second side of the isolation trench exhibits tensile stress.
15. The isolation structure of claim 13 , wherein the flowable dielectric is selected from a group consisting of borophosphosilicate (BPSG) glass and spin-on flowable oxide and wherein the capping dielectric is a high density oxide and further comprising a silicon nitride liner intermediate between the flowable dielectric and sidewalls of the isolation trench.