Current-mode memory cell
View Patent ↗Methods and corresponding systems for reading a memory cell include a first current sourced from a first current source into a summing node, wherein the first current source is coupled to a first reference. A second current is sourced from a second current source into the summing node, wherein the second current source is coupled to the first reference through a programmable fuse. A third current is sunk from the summing node with a current sink, wherein the current sink is coupled to a second reference, and wherein a third current limit is greater than a first current limit and less than the sum of the first current limit and the second current limit. A voltage at the summing node is output in response to the first current, the second current, and the third current. The first and second current sources, and the current sink can be current mirrors.
1. A method for reading a memory cell having a programmable fuse comprising:
sourcing a first current from a first current source into a summing node, wherein the first current source is coupled to a first reference, and the first current is less than a first value;
sourcing a second current from a second current source into the summing node, wherein the second current source is coupled to the first reference through the programmable fuse, and the second current is less than a second value;
sinking a third current from the summing node with a current sink, wherein the current sink is coupled to a second reference, and the third current is less than a third value, and wherein the third value is greater than the first value and less than the sum of the first value and the second value; and
outputting a voltage at the summing node in response to the first current, the second current, and the third current.
2. The method for reading a memory cell according to claim 1 wherein the sourcing the first current from the first current source comprises sourcing a first current from a first current source mirrored with a first bias current in a bias circuit.
3. The method for reading a memory cell according to claim 1 wherein the sinking the third current from the summing node with the current sink comprises sinking a third current from the summing node with a current sink mirrored with a second bias current in a bias circuit.
4. The method for reading a memory cell according to claim 1 :
wherein the sourcing the first current from the first current source comprises sourcing a first current from a first current source mirrored with a first bias current in a bias circuit;
wherein the sourcing the second current from the second current source comprises sourcing a second current from a second current source mirrored with the first bias current; and
wherein the sinking the third current from the summing node with the current sink comprises sinking a third current from the summing node with a current sink mirrored with a second bias current in a bias circuit.
5. The method for reading a memory cell according to claim 1 further comprising:
enabling the first current, the second current, and the third current in response to a read signal being in an asserted state; and
disabling the first current, the second current, and the third current in response to the read signal being in a non-asserted state.
6. The method for reading a memory cell according to claim 1 wherein the outputting a voltage at the summing node comprises:
outputting a higher voltage at the summing node to indicate the programmable fuse is not blown; and
outputting a lower voltage at the summing node to indicate the programmable fuse is blown.
7. The method for reading a memory cell according to claim 2 wherein the sourcing the second current from the second current source comprises sourcing a second current from a second current source mirrored with the first bias current.
8. The method for reading a memory cell according to claim 5 :
wherein the enabling the first current and the second current in response to the read signal being in the asserted state comprises enabling a first bias current in a first bias circuit and sourcing a first current from a first current source mirrored with the first bias current and sourcing a second current from a second current source mirrored with the first bias current; and
wherein the enabling the third current in response to the read signal being in the asserted state comprises enabling a second bias current in a second bias circuit and sinking a third current with a current sink mirrored with the second bias current.
9. A circuit for reading a programmable fuse state in a memory cell comprising:
a first current source coupled between a first reference and a current summing node, wherein the first current source is configured to provide a first current that is less than a first limit;
a second current source coupled to the current summing node;
a programmable fuse having a first terminal coupled to the first reference, and a second terminal coupled to the second current source, wherein the second current source is configured to provide a high second current that is less than a second limit when the programmable fuse is in a non-blown state, and wherein the second current source is configured to provide a low second current that is lower than the high second current and less than a fourth limit when the programmable fuse is in a blown state; and
a third current source coupled between the current summing node and a second reference, wherein the third current source is configured to provide a third current that is less than a third limit, and wherein the third limit is less than the sum of the first limit and the second limit, and the third limit is greater than the sum of the first limit and the fourth limit.
10. The circuit for reading a programmable fuse state according to claim 9 wherein the first current source comprises a second transistor of a first conductivity type having a first current electrode coupled to the first reference, and a second current electrode coupled to the summing node.
11. The circuit for reading a programmable fuse state according to claim 9 wherein the second current source comprises a first transistor of a first conductivity type having a first current electrode coupled to the second terminal of the programmable fuse, and a second current electrode coupled to the summing node.
12. The circuit for reading a programmable fuse state according to claim 9 wherein the third current source comprises a third transistor of a second conductivity type having a first current electrode coupled to the second reference, and a second current electrode coupled to the summing node.
13. The circuit for reading a programmable fuse state according to claim 9 wherein the first current source, the second current source, and the third current source are configured as a first current mirror, a second current mirror, and a third current mirror, respectively.
14. The circuit for reading a programmable fuse state according to claim 13 wherein the first current mirror comprises a first transistor coupled to a fourth transistor in a current mirror configuration, and wherein the second current mirror comprises the first transistor coupled to the fourth transistor in a current mirror configuration, and wherein the third current mirror comprises a third transistor coupled to a fifth transistor in a current mirror configuration.
15. A circuit for reading a state of a memory cell having a programmable fuse comprising:
a programmable fuse having a first terminal coupled to a first reference, and a second terminal;
a first transistor, of a first conductivity type, having a first current electrode coupled to the second terminal of the programmable fuse, a second current electrode, and a control electrode;
a second transistor, of a first conductivity type, having a first current electrode coupled to the first reference, a second current electrode, and a control electrode coupled to the control electrode of the first transistor;
a summing node coupled to the second current electrode of the first transistor and the second current electrode of the second transistor; and
a third transistor, of a second conductivity type, having a first current electrode coupled to a second reference, a second current electrode coupled to the summing node, and a control electrode, whereby a voltage at the summing node corresponds to the state of the memory cell.
16. The circuit for reading a state of a programmable fuse according to claim 15 comprising a fourth transistor, of a first conductivity type, coupled to the first and second transistors in a current mirror configuration for controlling current through the first and second transistors.
17. The circuit for reading a state of a programmable fuse according to claim 15 comprising a fifth transistor coupled to the third transistor in a current mirror configuration for controlling current through the third transistor.
18. The circuit for reading a state of a programmable fuse according to claim 15 further comprising a bias circuit for controlling a first current in the first transistor, a second current in the second transistor, and a third current in the third transistor, wherein the bias circuit provides voltages for limiting the first current to a first limit, limiting the second current to a second limit, and limiting the third current to a third limit, and wherein the third limit is greater than the first limit, and the third limit is less than the sum of the first limit and the second limit.
19. The circuit for reading a state of a programmable fuse according to claim 16 wherein the fourth transistor has a first current electrode coupled to the first reference, a second current electrode, and a control electrode coupled to the second current electrode of the fourth transistor, and the control electrodes of the first and second transistors.
20. The circuit for reading a state of a programmable fuse according to claim 17 wherein the fifth transistor has a first current electrode, a second current electrode coupled to the second reference, and a control electrode coupled to the first current electrode of the fifth transistor, and the control electrode of the third transistor.