Granted Patent B2

US 7,679,125 · App. 11/300,077 · Granted Mar 16, 2010

Abstract

Claims (27)

1. A semiconductor device structure, comprising:

a substrate;

a gate over the substrate;

a storage layer over the gate;

a channel region over the storage layer;

source/drain regions laterally adjacent to the channel; and

a conductive region over and in direct contact with the channel region and overlapping the channel region.

2. The semiconductor device of claim 1 , wherein the storage layer comprises nanocrystals.

3. The semiconductor device of claim 1 further comprising a sidewall spacer laterally adjacent to the conductive region.

4. The semiconductor device of claim 1 , wherein the conductive region comprises means for a well contact.

5. The semiconductor device of claim 1 , wherein the conductive region comprises polysilicon and the channel region comprises monocrystalline silicon.

6. The semiconductor device of claim 1 further comprising silicide layers on the gate and the source/drains.

7. The semiconductor device of claim 1 , wherein the source/drain regions comprise monocrystalline regions adjacent to the channel and polysilicon regions adjacent to the monocrystalline regions.

8. A non-volatile memory cell, comprising:

a substrate;

a control gate on the substrate;

a storage layer on the control gate;

a monocrystalline channel region on the storage layer; and

a conductive region extending upward from the channel region for removing minority carriers from the channel.

9. The non-volatile memory cell of claim 8 , wherein the conductive region is further characterized as being polycrystalline.

10. The non-volatile memory cell of claim 8 , wherein the control gate comprises polysilicon.

11. The non-volatile memory cell of claim 8 , wherein the storage layer comprises nanocrystals.

12. The non-volatile memory cell of claim 8 further comprising:

a drain on a first side of the channel; and

a source on a second side of the channel, wherein the source and drain are monocrystalline adjacent to the channel.

13. The non-volatile memory of claim 8 , further comprising a first silicide layer on a portion of the source, a second silicide layer on a portion of the drain, and a third silicide layer on a portion of the conductive region.

14. The non-volatile memory cell of claim 8 further comprising a sidewall spacer adjacent to a side of the conductive region.

Assignments (41)