Memory with fault tolerant reference circuitry
View Patent ↗A memory not only uses redundant cells but also redundant references to reduce the likelihood of a failure. In one approach a failure in a reference can cause both the primary cell as well as the redundant cell to be ineffective. To overcome this potential problem two references for each bit are employed. In one form, the primary cell of a first bit is compared to one reference and the redundant cell of the first bit is compared to another reference. The primary and redundant cell of a second bit can use these two references as well. In another aspect, two references are placed in parallel for both the primary and redundant cell of the bit.
1. A memory comprising a plurality of bits, each bit comprising:
a cell for being programmed to store either a logic one or a logic zero value;
a reference element comprising one or more reference cells having an output for providing a reference value;
a redundant cell for being programmed to store a same bit value as the cell;
a redundant reference element comprising one or more reference cells having an output for providing a reference value;
a first sense amplifier circuitry coupled to the cell and the output of the reference element, the sense amplifier circuitry having an output representative of either a current relationship or a voltage relationship between the cell and the reference element;
a second sense amplifier circuitry coupled to the redundant cell and the output of the redundant reference element, the second sense amplifier representative of either a current relationship or a voltage relationship between the redundant cell and the redundant reference element;
a logic circuit coupled to the output of the first sense amplifier circuitry and the output of the second sense amplifier circuitry, the logic circuit performing a logic operation on the outputs of the first and second sense amplifier circuitry and providing an output indicating a result of the logic operation as a logic state of the bit.
2. The memory of claim 1
wherein the redundant reference element is coupled in parallel with the reference element.
3. The memory of claim 2 wherein the redundant reference element is physically positioned between the reference element and the redundant cell.
4. The memory of claim 2 wherein redundant reference element is physically positioned away from the reference element to reduce a probability of error resulting from wafer processing defects occurring in both the reference element and the redundant reference element.
5. The memory of claim 1 wherein:
the memory cell has a dominant failure mode of remaining at a logic low when programmed to be a logic high; and
the reference element has a dominant failure mode of having a higher resistance than desired.
6. The memory of claim 5 wherein:
the redundant memory cell has a dominant failure mode of remaining at a logic low when programmed to be a logic high; and
the redundant reference element has a dominant failure mode of having a higher resistance than desired.
7. The memory of claim 5 wherein the logic circuit of the memory is further characterized by the logic function being an OR function.
8. The memory of claim 1 wherein the logic function of the logic circuit depends upon a type of processing failure associated with the cell and the reference element.
9. The memory of claim 1 wherein the one or more cells of the reference element comprise one or more segment(s) of silicided polysilicon material.
10. The memory of claim 1 wherein the one or more cells of the reference element comprise one or more segment(s) of polysilicon material.
11. The memory of claim 1 wherein the memory cell comprises a resistive material, the resistive material being open-circuited when programmed and being conductive when not programmed.
12. A method of determining a bit logic state of a bit of a memory comprising:
attempting to program a memory cell of the bit to store either a logic one or a logic zero value;
providing a reference value from a reference element of the bit, the reference element of the first bit comprising one or more cells;
attempting to program a redundant cell of the bit to store a same bit value as the cell of the first bit;
providing a redundant reference value from a redundant reference element of the bit, the redundant reference element of the bit comprising one or more cells;
sensing a cell logic state using the cell of the bit and the reference element of the bit;
sensing a redundant cell logic state using the redundant cell of the bit and the redundant reference element;
producing an output indicating the logic state of the bit in response to performing a logic operation on the combination of the cell logic state and the redundant cell logic state.
13. The method of claim 12 further comprising:
placing the redundant reference element in parallel with the reference element.
14. The method of claim 12 wherein:
the step of sensing the cell logic state is further characterized by coupling the cell of the bit and the reference element of the bit to a first sense amplifier associated with the first bit; and
the step of sensing the redundant cell logic state is further characterized by coupling the redundant reference element and the redundant cell of the bit to a second sense amplifier associated with the bit.
15. The method of claim 12 further comprising: physically positioning the redundant reference element of the bit between the reference element of the bit and the redundant cell of the bit.
16. The method of claim 12 further comprising:
physically positioning the redundant reference element away from the reference element.
17. A memory comprising:
a cell associated with a first bit having a first terminal coupled to a voltage terminal, and having a second terminal;
a reference element associated with both the first bit and a second bit having a first terminal coupled to the voltage terminal, and having a second terminal;
a cell associated with the second bit having a first terminal coupled to the voltage terminal, and having a second terminal;
a redundant cell associated with the first bit having a first terminal coupled to the voltage terminal, and having a second terminal;
an additional reference element associated with both the first bit and the second bit having a first terminal coupled to the voltage terminal, and having a second terminal;
a redundant cell associated with the second bit having a first terminal coupled to the voltage terminal, and having a second terminal;
a first sense amplifier having a first input coupled to the second terminal of the cell associated with the first bit, a second input coupled to the second terminal of the reference element associated with the first bit and the second bit, and having an output;
a second sense amplifier having a first input coupled to the second terminal of the reference element associated with both the first bit and the second bit, a second input coupled to the second terminal of the cell associated with the second bit, and an output;
a third sense amplifier having a first input coupled to the second terminal of the redundant cell associated with the first bit, a second input coupled to the second terminal of the additional reference element associated with both the first bit and the second bit, and an output;
a fourth sense amplifier having a first input coupled to the second terminal of the additional reference element associated with both the first bit and the second bit, a second input coupled to the redundant cell associated with the second bit, and an output; and
logic circuitry coupled to the first sense amplifier, the second sense amplifier, the third sense amplifier and the fourth sense amplifier, the logic circuit performing a first logic operation of a first type on the outputs of the first and second sense amplifiers and performing a second logic operation of the first type on the outputs of the third and fourth sense amplifiers and providing outputs representative of the first and second logic operations as indicating whether the cell associated with the first bit and the cell associated with the second bit are programmed with either a logic one or a logic zero value.
18. The memory of claim 17 wherein the cell associated with the first bit, the redundant cell associated with the first bit, the cell associated with the second bit, and the redundant cell associated with the second bit each comprise a segment of silicided polysilicon material and the reference element associated with both the first bit and the second bit and the additional reference element associated with both the first bit and the second bit each comprise one or more segment(s) of silicided polysilicon material.
19. A memory comprising:
a cell associated with a first bit having a first terminal coupled to a voltage terminal, and having a second terminal;
a reference element associated with the first bit and having a first terminal coupled to the voltage terminal, and having a second terminal;
an additional reference element associated with the first bit and having a first terminal coupled to the voltage terminal, and having a second terminal;
a redundant cell having a first terminal coupled to the voltage terminal and a second terminal;
a first sense amplifier having a first input coupled to the second terminal of the cell associated with the first bit, a second input coupled to both the second terminal of the reference element associated with the first bit and the second terminal of the additional reference element, and having an output;
a second sense amplifier having a first input coupled to both the second terminal of the reference element associated with the first bit and the second terminal of the additional reference element, a second input coupled to the second terminal of the redundant cell, and an output; and
logic circuitry coupled to the output of the first sense amplifier and the output of the second sense amplifier, the logic circuit performing a logic operation on the outputs of the first and second sense amplifiers and providing an output representative of the logic operation as indicating whether the cell associated with the first bit is programmed with either a logic one or a logic zero value.
20. The memory of claim 19 wherein the additional reference element is physically positioned away from the reference element to reduce a probability of error resulting from wafer processing defects occurring in both the reference element of the first bit and the additional reference element.