IP Library Granted Patent US 7,741,195
Granted Patent B2
US 7,741,195 · App. 11/420,551 · Granted Jun 22, 2010

Method of stimulating die circuitry and structure therefor

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Quick Facts
Patent No.
US 7,741,195
App. No.
11/420,551
Granted
Jun 22, 2010
Kind
B2
Abstract

A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.

Claims (38)

1. A method comprising:

providing a wafer having a first die and a scribe grid, the first die having die circuitry and a bond pad electrically connected to the die circuitry, the scribe grid having a scribe grid pad electrically connected to the die circuitry;

accessing the scribe grid pad to stimulate the die circuitry; and

disconnecting the die circuitry from the scribe grid pad prior to singulation.

2. The method of claim 1 , wherein providing the wafer comprises:

forming the die circuitry;

forming a plurality of conductive layers electrically connected to the die circuitry;

forming the bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality conductive layers; and

forming the scribe grid pad in the scribe grid electrically connected to the die circuitry via at least one conductive layer of the plurality conductive layers.

3. The method of claim 1 , wherein providing the wafer comprises providing the wafer having the scribe grid, wherein the scribe grid further comprises scribe grid circuitry electrically connected to the scribe grid pad.

4. The method of claim 3 , wherein providing the wafer comprises providing the wafer having the scribe grid circuitry, wherein the scribe grid circuitry comprises only passive circuitry.

5. The method of claim 3 , wherein providing the wafer comprises providing the wafer having the scribe grid circuitry, wherein the scribe grid circuitry comprises active circuitry.

6. The method of claim 3 , further comprising accessing the scribe grid pad to test the scribe grid circuitry.

7. The method of claim 1 , wherein providing the wafer comprises providing the wafer, wherein the wafer has a second die, the second die having second die circuitry, wherein the scribe grid pad is electrically connected to the second die circuitry.

8. The method of claim 1 , further comprising singulating and packaging the first die.

9. The method of claim 1 , wherein providing the wafer comprises:

forming an interconnect extending from a conductive layer of the first die to a conductive layer of the scribe grid, wherein the bond pad is over the conductive layer of the first die and the scribe grid pad is over the conductive layer of the scribe grid, and the interconnect electrically connects the die circuitry to the scribe grid pad.

10. The method of claim 1 , wherein providing the wafer comprises:

forming an interconnect over at least a portion of the bond pad and over at least a portion of the scribe grid pad, wherein the interconnect electrically connects the bond pad to the scribe grid pad.

11. The method of claim 1 , wherein scribe grid pad is electrically connected to the die circuitry of the first die in a layer underlying the top surface of the wafer.

12. A method comprising:

receiving a wafer having a plurality of die and a scribe grid, a first die of the plurality of die having die circuitry and a bond pad electrically connected to the die circuitry, and the scribe grid having a scribe grid pad electrically connected to the die circuitry of the first die;

disconnecting the scribe grid pad from the die circuitry of the first die;

subsequently singulating the plurality of die; and

packaging at least one die of the plurality of die.

13. The method of claim 12 , wherein scribe grid pad is electrically connected to the die circuitry of the first die in a layer underlying the top surface of the wafer.

14. The method of claim 12 , wherein providing the wafer comprises:

forming the die circuitry;

forming a plurality of conductive layers electrically connected to the die circuitry;

forming the bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality conductive layers; and

forming the scribe grid pad in the scribe grid electrically connected to the die circuitry via at least one conductive layer of the plurality conductive layers.

15. The method of claim 12 , wherein providing the wafer comprises providing the wafer having the scribe grid, wherein the scribe grid further comprises scribe grid circuitry electrically connected to the scribe grid pad.

16. The method of claim 15 , wherein providing the wafer comprises providing the wafer having the scribe grid circuitry, wherein the scribe grid circuitry comprises only passive circuitry.

17. The method of claim 15 , wherein providing the wafer comprises providing the wafer having the scribe grid circuitry, wherein the scribe grid circuitry comprises active circuitry.

18. The method of claim 15 , further comprising accessing the scribe grid pad to test the scribe grid circuitry.

19. The method of claim 12 , wherein providing the wafer comprises providing the wafer, wherein the wafer has a second die, the second die having second die circuitry, wherein the scribe grid pad is electrically connected to the second die circuitry.

20. The method of claim 12 , wherein providing the wafer comprises:

forming an interconnect extending from a conductive layer of the first die to a conductive layer of the scribe grid, wherein the bond pad is over the conductive layer of the first die and the scribe grid pad is over the conductive layer of the scribe grid, and the interconnect electrically connects the die circuitry to the scribe grid pad.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Mar 15, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 024085/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 26, 2006
From: RASHID, MOHAMMED K.; RASHED, MAHBUB M.; ROTH, SCOTT S.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 017684/0311 →