Memory with charge storage locations
View Patent ↗A method for operating a memory device includes selecting a cell comprising an array of word lines, selecting a word line within said array and applying an operating voltage to said selected word line. A shielding voltage is also applied to the closest adjacent facing word line of said selected word line. This may prevent unintended, program, read, or erase of said unselected word line. The remainder of unselected word lines can be floated.
1. A method for erasing a memory device, the method comprising:
selecting a cell comprising an array of word lines;
selecting a word line within said array, wherein the array consists of said selected word line, a closest adjacent facing word line of said selected word line, and unselected word lines;
applying an operating voltage to said selected word line;
applying a shielding voltage to said closest adjacent facing word line of said selected word line; and
floating the unselected world lines of said array while applying the operating voltage to said selected word line.
2. The method of claim 1 , wherein said selected word line has a closest, adjacent non-facing word that has an applied voltage.
3. The method of claim 2 , wherein said closest, adjacent non-facing word line has an applied voltage between approximately 0 volts and −7 volts.
4. The method of claim 1 , wherein said operating voltage is between approximately 1 volt and 7 volts.
5. The method of claim 1 , wherein said method for operating said memory device is a method for operating a nonvolatile charge storage device.
6. The method of claim 1 , wherein said method for operating said memory device is a method for operating a nanocrystalline FinFET flash device.
7. A method for erasing a memory device, the method comprising:
selecting a cell comprising an array of word lines;
selecting a word line within said array;
applying a first operating voltage to said selected word line;
applying a first shielding voltage to the closest adjacent facing word line of said selected word line;
applying a second operating voltage to an adjacent word line of said selected word line;
applying a second shielding voltage to the closest adjacent facing word line of said adjacent word line; and
floating the remainder of the unselected word lines of the array while applying the first operating voltage to said selected word line.
8. The method of claim 7 , wherein said first shielding voltage is approximately equal to said second shielding voltage.
9. The method of claim 8 , wherein said first shielding voltage is between approximately 0 volts and −5 volts.
10. The method of claim 7 , wherein said first operating voltage is between approximately 1 volt and 7 volts.
11. The method of claim 7 , wherein said selected word line has a closest, adjacent non-facing word line.
12. The method of claim 11 , wherein said closest, adjacent non-facing word line has an applied voltage between approximately 0 volts and −7 volts.
13. The method of claim 7 , wherein said method for operating said memory device is a method for operating a nonvolatile charge storage device.
14. The method of claim 7 , wherein said method for operating said memory device is a method for operating a nanocrystalline FinFET flash device.
15. The method of claim 1 , wherein the array is a NOR array.