IP Library Granted Patent US 7,868,389
Granted Patent B2
US 7,868,389 · App. 11/928,314 · Granted Jan 11, 2011

Electronic device comprising a gate electrode including a metal-containing layer having one or more impurities

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Quick Facts
Patent No.
US 7,868,389
App. No.
11/928,314
Granted
Jan 11, 2011
Kind
B2
Abstract

One or more impurities may be incorporated within a metal-containing layer of a metal-containing gate electrode to modify the work function of the metal-containing gate electrode of a transistor can affect the threshold voltage of the transistor. In one embodiment, the impurity can be used in a p-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the valence band for silicon. In another embodiment, the impurity can be used in an n-channel transistor to allow the work function of a metal-containing gate electrode to be closer to the conduction band for silicon. In a particular embodiment, a boron-containing species is implanted into a metal-containing layer within the metal-containing gate electrode within a p-channel transistor, so that the metal-containing gate electrode has a work function closer to the valence band for silicon as compared to the metal-containing gate electrode without the boron-containing species.

Claims (72)

1. An electronic device comprising:

a substrate including a first portion and a second portion;

a gate dielectric layer overlying the first portion and the second portion of the substrate;

a first gate electrode overlying the gate dielectric layer and the first portion of the substrate, wherein:

the first gate electrode includes a first portion of a first layer, a first portion of a second layer, and a first portion of a third layer, wherein the second layer lies between the first layer and the third layer;

the first portion of the first layer lies immediately adjacent to the gate dielectric layer; and

the first layer comprises a first element that is a metallic element and an impurity that includes a second element within Group 2 or 13 of the Periodic Table;

a first source/drain region overlying the first portion of the substrate, wherein a first transistor includes the first source/drain and the first gate electrode;

a second gate electrode overlying the gate dielectric layer and the second portion of the substrate, wherein:

the second gate electrode includes a second portion of the second layer and a second portion of the third layer; and

the second portion of the second layer lies immediately adjacent to the gate dielectric layer; and

a second source/drain region overlying the second portion of the substrate, wherein a second transistor includes the second source/drain and the second gate electrode.

2. The electronic device of claim 1 , wherein the impurity comprises a boron-containing species.

3. The electronic device of claim 1 , wherein the second gate electrode does not include the first layer.

4. The electronic device of claim 1 , wherein:

the first transistor is a PMOS transistor;

the first layer substantially determines a work function of the PMOS transistor;

the second transistor is an NMOS transistor; and

the second layer substantially determines a work function of the NMOS transistor.

5. An electronic device comprising:

a substrate including a first portion and a second portion;

a first transistor overlying the first portion of the substrate, wherein the first transistor includes:

a first channel region;

a first gate dielectric layer overlying the first channel region; and

a first gate electrode overlying the first gate dielectric layer, wherein:

the first gate electrode includes a first layer lying immediately adjacent to the first gate dielectric layer; and

the first layer includes:

a first element that is a first transition metal element; and

a second element that is an element within Group 2 or 13 of the Periodic Table; and

a second transistor overlying the second portion of the substrate, wherein the second transistor includes:

a second channel region;

a second gate dielectric layer overlying the second channel region; and

a second gate electrode overlying the second gate dielectric layer, wherein:

the second gate electrode includes a second layer; and

the second layer includes a third element that is a second transition metal element, and the second layer does not include boron.

6. The electronic device of claim 5 , wherein the second element is boron.

7. The electronic device of claim 5 , wherein the first transition metal element is different from the second transition metal element.

8. The electronic device of claim 7 , wherein the first gate dielectric layer and the second gate dielectric layer are different portions of a same gate dielectric layer.

9. The electronic device of claim 5 , wherein each of the first gate dielectric layer and the second gate dielectric layer includes hafnium, zirconium, or any combination thereof.

10. The electronic device of claim 5 , wherein the first layer comprises a fourth element other than silicon, wherein the fourth element is different from the first and second elements.

11. The electronic device of claim 5 , wherein the first transistor is a PMOS transistor, and

the second transistor is an NMOS transistor.

12. The electronic device of claim 11 , wherein the first layer comprises TiN, and

the third layer comprises TaSiN.

13. The electronic device of claim 5 , wherein the first gate electrode does not include the second layer, and the second gate electrode does not include the first layer.

14. An electronic device comprising:

a substrate including a first portion and a second portion;

a gate dielectric layer overlying the first portion and the second portion of the substrate;

a first transistor overlying the first portion of the substrate and comprising a first gate electrode and a first source/drain region, wherein:

the first gate electrode overlies the gate dielectric layer;

the first gate electrode includes a first layer and a second layer;

the first layer includes a first metallic element and substantially determines a work function for the first electrode; and

the first source/drain region lies adjacent to the first gate electrode; and

a second transistor overlying the second portion of the substrate and comprising a second gate electrode and a second source/drain region, wherein:

the second gate electrode overlies the gate dielectric layer;

the second gate electrode includes the second layer and a third layer;

the third layer includes a second metallic element and a boron-containing species, and the third layer substantially determines a work function of the second gate electrode; and

the second source/drain region lies adjacent to the second gate electrode, wherein:

the first metallic element is different from the second metallic element; and

the first layer does not include the second metallic element. or the third layer does not include the first metallic element.

15. The electronic device of claim 14 , wherein the second layer comprises an elemental transition metal, a transition metal nitride, a transition metal silicon nitride, or any combination thereof.

16. The electronic device of claim 14 , wherein:

the first transistor is a NMOS transistor;

the first layer lies immediately adjacent to the gate dielectric layer;

the second transistor is a PMOS transistor; and

the third layer lies immediately adjacent to the gate dielectric layer.

17. The electronic device of claim 16 , wherein first gate electrode does not include the third layer, and the second gate electrode does not include the first layer.

18. The electronic device of claim 16 , wherein first gate electrode includes the third layer, and the second gate electrode does not include the first layer,

19. The electronic device of claim 16 , wherein the first gate electrode includes a different number of layers as compared to the second gate electrode,

20. The electronic device of claim 14 , wherein:

the first metallic element includes Ta, Hf, Nb, or NiSi; and

the second metallic element includes Ti, Mo, Ru, Ir, or Mo.

Assignments (30)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
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To: NXP B.V.
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From: NXP B.V.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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To: NXP B.V.
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