Virtual direct memory access (DMA) channel technique with multiple engines for DMA controller
View Patent ↗A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.
1. A method of managing direct memory access (DMA) resources in a system that provides plural DMA engines, the method comprising:
associating context information, including DMA parameters, with each of plural virtual DMA channels, the virtual DMA channels more numerous than the plural DMA engines;
for at least a current subset of less than all the virtual DMA channels, caching the associated context information with respective ones of the plural DMA engines;
and switching amongst the plural DMA engines, and therefore amongst respective ones of the current subset of virtual DMA channels, without latency associated with saving or restoring context information.
2. The method of claim 1 , further comprising:
saving and restoring context information for respective ones of the virtual DMA channels to and from a DMA channel buffer, thereby updating the current subset of virtual DMA channels for which context information is cached with a respective DMA engine.
3. The method of claim 1 , further comprising:
performing the saving and restoring if a next runnable one of the virtual DMA channels is not a member of the current subset.
4. The method of claim 1 , further comprising:
performing the saving and restoring while a prior runnable one of the virtual DMA channels is active, such that context information for a next runnable virtual DMA channel is cached with a respective DMA engine and available for activation without context switch latency.
5. The method of claim 1 , further comprising maintaining the current subset of virtual DMA channels so that respective DMA engines cache context information for one of:
a most frequently used subset of the virtual DMA channels;
a most recently used subset of the virtual DMA channels;
a subset of the virtual DMA channels selected based on a set- or frame-oriented implementation of a frequency of use policy; and
a subset of the virtual DMA channels selected based on a set- or frame-oriented implementation of a recency of use policy.
6. The method of claim 1 ,
wherein, at any given time, each of the virtual DMA channels is mapped to a respective DMA engine, either as a member of the current subset for which context information is cached or as an uncached entry in a DMA channel buffer.
7. The method of claim 1 ,
wherein a single one of the DMA engines and an associated single one of the virtual DMA channels is active at any given time.
8. The method of claim 1 ,
wherein the switching amongst the DMA engines occurs in about one DMA clock cycle, and
wherein the saving and restoring, if necessary, has a multi-cycle latency.
9. An apparatus comprising:
a Direct Memory Access (DMA) controller suitable for coupling to a DMA channel buffer that stores context information, including DMA parameters, for each of plural virtual DMA channels;
the DMA controller including plural DMA engines each configured to cache context information for a respective one of the virtual DMA channels that together constitute a current subset thereof, the virtual DMA channels more numerous than the plural DMA engines;
and the DMA controller including a context switching controller configured to switch amongst the plural DMA engines without substantial context switch latency as long as a next runnable one of the virtual DMA channels is within the current subset for which context information is cached with a respective one of the plural DMA engines.
10. The apparatus of claim 9 ,
wherein, if the next runnable one of the virtual DMA channels is not within the current subset, the context switching controller is configured to load a selected one of the DMA engines with context information retrieved from the DMA channel buffer.
11. The apparatus of claim 10 ,
the load has a multi-cycle latency.
12. The apparatus of claim 10 ,
wherein, coincident with the load, the context switching controller saves to the DMA channel buffer context information for at least one of the virtual DMA channels of a previously current subset thereof.
13. The apparatus of claim 10 ,
wherein the context switching controller initiates the load while a prior runnable one of the virtual DMA channels remains active, such that context information for a next runnable virtual DMA channel is cached with a respective DMA engine and available for activation without context switch latency.
14. The apparatus of claim 9 ,
wherein the context switching controller is configured to save and restore context information for respective ones of the virtual DMA channels to and from a DMA channel buffer, thereby updating the current subset of virtual DMA channels for which context information is cached with a respective DMA engine.
15. The apparatus of claim 9 ,
wherein the context switching controller implements a replacement policy that caches in respective ones of the DMA engines context information for one of:
a most frequently used subset of the virtual DMA channels;
a most recently used subset of the virtual DMA channels;
a subset of the virtual DMA channels selected based on a set- or frame-oriented implementation of a frequency of use policy; and
a subset of the virtual DMA channels selected based on a set- or frame-oriented implementation of a recency of use policy.
16. The apparatus of claim 9 ,
wherein a single one of the DMA engines and an associated single one of the virtual DMA channels is active at any given time.
17. The apparatus of claim 9 , further comprising:
a processor; memory; and a data transfer pathway between memory and plural peripherals, each operatively coupled to the DMA controller.
18. The apparatus of claim 17 ,
wherein the DMA channel buffer resides in the memory.
19. The apparatus of claim 17 , embodied as a system on a chip.
20. An electronic device comprising:
a processor and memory accessible thereto;
a DMA interconnect coupling the memory and plural devices;
and a DMA controller that interfaces with the DMA interconnect and coordinates plural DMA engines to support plural virtual DMA channels, the virtual DMA channels more numerous than the plural DMA engines, the DMA controller caching associated context information, including DMA parameters, for at least a current subset of less than all the virtual DMA channels, the DMA controller including logic to switch amongst the plural DMA engines, and therefore amongst respective ones of the current subset of virtual DMA channels, without latency associated with saving or restoring context information.