Low voltage circuit with variable substrate bias
View Patent ↗In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.
1. A circuit comprising:
a first transistor of a first conductivity type having a first current electrode coupled to an output terminal, a control electrode coupled to an input signal terminal, a second current electrode, and a bulk having a substrate connection terminal connected directly to the second current electrode;
a second transistor of the first conductivity type having a first current electrode coupled to the output terminal, a control electrode coupled to the control electrode of the first transistor, a second current electrode coupled to a voltage terminal, and a bulk having a substrate connection terminal connected directly to the substrate connection terminal of the first transistor;
a resistive load coupled between the second current electrode of the first transistor and the voltage terminal; and
output drive circuitry coupled to the output terminal.
2. The circuit of claim 1 further comprising:
a third transistor having a first current electrode coupled to the output terminal, a control electrode connected to the first current electrode thereof, a second current electrode connected to the first current electrode of the first transistor, and a bulk having a substrate connection terminal connected directly to the substrate connection terminal of both the first transistor and the second transistor.
3. The circuit of claim 1 wherein the output drive circuitry further comprises:
a third transistor of a second conductivity type opposite the first conductivity type having a first current electrode coupled to a second voltage terminal, a second current electrode coupled to the output terminal and a control electrode coupled to the input signal terminal.
4. The circuit of claim 1 wherein the output drive circuitry further comprises:
a third transistor of a second conductivity type opposite the first conductivity type having a first current electrode coupled to a second voltage terminal, a second current electrode coupled to the output terminal and a control electrode coupled to a complementary output terminal; and
a fourth transistor of the second conductivity type having a first current electrode coupled to the second voltage terminal, a second current electrode coupled to the complementary output terminal and a control electrode coupled to the output terminal.
5. The circuit of claim 4 further comprising:
a fifth transistor of the first conductivity type having a first current electrode coupled to the complementary output terminal, a control electrode coupled to a complement input signal terminal, a second current electrode, and a bulk having a substrate connection terminal connected directly to the second current electrode thereof;
a sixth transistor of the first conductivity type having a first current electrode coupled to the complementary output terminal, a control electrode coupled to the control electrode of the fifth transistor, a second current electrode coupled to the voltage terminal, and a bulk having a substrate connection terminal connected directly to the substrate connection terminal of the fifth transistor; and
a second resistive load coupled between the second current electrode of the fifth transistor and the voltage terminal.
6. The circuit of claim 5 wherein the first conductivity type is N conductivity and the second conductivity type is P conductivity.
7. The circuit of claim 5 wherein the output drive circuitry further comprises:
a pair of cross-coupled transistors of a second conductivity type opposite the first conductivity type, the pair of cross-coupled transistors respectively providing drive current for true and complement outputs of the circuit.
8. The circuit of claim 1 wherein the resistive load is one of either a transistor or a polysilicon resistor.
9. A circuit comprising a bias stage having an input signal terminal for receiving an input signal, the circuit modifying the input signal with a drive stage to provide an output signal in complement form, comprising:
a load;
a drive transistor in the drive stage of the circuit, the drive transistor having a bulk connected to a terminal of the load and a control electrode coupled to the input signal terminal; and
a bias transistor in the bias stage of the circuit, the bias transistor having a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor, the bias transistor having a control electrode coupled to the input signal terminal, the bias transistor having a current electrode directly connected to both the terminal of the load and to the bulk of the bias transistor, wherein voltage applied to the bulk of the drive transistor and the bulk of the bias transistor varies in response to the input signal.
10. The circuit of claim 9 further comprising:
a level shifting transistor having a first current electrode coupled in series between an output terminal and the bias transistor, the level shifting transistor having a control electrode and first current electrode connected together and to the output terminal, a second current electrode coupled to the bias transistor, and a bulk that is coupled to the bulk of the bias transistor and to the bulk of the drive transistor.
11. The circuit of claim 9 wherein the drive stage further comprises:
a pull-up transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode coupled to the input signal terminal and a second current electrode coupled to the output terminal.
12. The circuit of claim 9 further comprising:
a second bias stage, a second load and a second drive stage for providing an output signal wherein each of the second bias stage and the second drive stage comprises a transistor having a control electrode coupled to a complement input signal terminal and having a bulk connected together and to a terminal of the second load.
13. The circuit of claim 12 wherein the drive stage has a first pull-up transistor that is biased by the output signal and the second drive stage has a second pull-up transistor that is biased by the output signal in complement form.
14. The circuit of claim 12 wherein the load and the second load comprise both resistance and reactance.
15. The circuit of claim 9 wherein the load is one of either a transistor or a polysilicon resistor.
16. A circuit comprising:
a load having a first terminal coupled to a first voltage terminal and having a second terminal;
a first transistor having a control electrode coupled to an input signal terminal, a first current electrode coupled to a complementary output terminal and both a second current electrode and a bulk connected together and to the second terminal of the load;
a second transistor having a control electrode coupled to the input signal terminal, a first current electrode coupled to the first voltage terminal, a second current electrode coupled to the complementary output terminal, and a bulk connected to the bulk of the first transistor; and
a pull-up transistor coupled in series with the second transistor, said pull-up transistor located between a second voltage terminal and the complementary output terminal.
17. The circuit of claim 16 further comprising:
a third transistor for level shifting, the third transistor having a first current electrode coupled to the complementary output terminal, a second current electrode coupled to the first current electrode of the first transistor, a control electrode connected to the first current electrode thereof, and a bulk connected to the bulk of both the first transistor and the second transistor.
18. The circuit of claim 16 wherein the first transistor and the second transistor have a first conductivity type and the pull-up transistor has a second conductivity type opposite the first conductivity type.
19. The circuit of claim 16 wherein the load comprises primarily a resistive load.
20. The circuit of claim 16 further comprising:
a second load having a first terminal coupled to the first voltage terminal and having a second terminal;
a third transistor having a control electrode coupled to a complement input signal terminal, a first current electrode coupled to a true output terminal and both a second current electrode and a bulk connected together and to the second terminal of the second load;
a fourth transistor having a control electrode coupled to the complement input signal, a first current electrode coupled to the first voltage terminal, a second current electrode coupled to the true output terminal, and a bulk connected to the bulk of the third transistor; and
a second pull-up transistor coupled in series with the fourth transistor, said second pull-up transistor located between the second voltage terminal and the true output terminal.
21. The circuit of claim 20 wherein the pull-up transistor and the second pull-up transistor comprise cross-coupled control gates wherein a control gate of the pull-up transistor is coupled to the true output terminal and a control gate of the second pull-up transistor is coupled to the complementary output terminal.
22. The circuit of claim 16 wherein a threshold voltage of the first transistor and a threshold voltage of the second transistor is reduced in response to an increase in magnitude of an input signal applied to the input signal terminal.
23. The circuit of claim 16 , wherein the load is one of either a transistor or a polysilicon resistor.