Integrated circuit with multiple independent gate field effect transistor (MIGFET) rail clamp circuit
View Patent ↗A rail clamp circuit ( 100 ) includes first and second power supply voltage rails, a multiple independent gate field effect transistor (MIGFET) ( 128 ), and an ESD event detector circuit ( 138 ). The MIGFET ( 128 ) has a source/drain path coupled between the first ( 112 ) and second ( 114 ) power supply voltage rails, and first and second gates. The ESD event detector circuit ( 138 ) is coupled between the first ( 112 ) and second ( 114 ) power supply voltage rails, and has first and second output terminals respectively coupled to the first and second gates of the MIGFET. In response to an electrostatic discharge (ESD) event between the first ( 112 ) and second ( 114 ) power supply voltage rails, the ESD event detector circuit ( 138 ) provides a voltage to the second gate to lower an absolute threshold voltage of the MIGFET ( 128 ) while providing a voltage to the first gate above the absolute threshold voltage so lowered, thereby making the MIGFET ( 128 ) conductive with relatively high conductivity.
1. For use with a plurality of external terminals of an integrated circuit that may be exposed to an electrostatic discharge (ESD) event, a rail clamp circuit comprising:
a first power supply voltage rail;
a second power supply voltage rail;
a multiple independent gate field effect transistor (MIGFET) having a source/drain path coupled between said first and second power supply voltage rails, a first gate and a second gate; and
an ESD event detector circuit coupled between said first and second power supply voltage rails, and having first and second output terminals respectively coupled to said first and second gates of said MIGFET, wherein in response to an ESD event between said first and second power supply voltage rails, said ESD event detector circuit provides a voltage to said first gate to adjust a threshold voltage of said MIGFET while providing a voltage to said second gate to make said MIGFET conductive with relatively high conductivity.
2. The rail clamp circuit of claim 1 wherein said MIGFET is formed above a substrate of the integrated circuit.
3. The rail clamp circuit of claim 2 wherein said MIGFET has a vertical channel and current flows horizontally with respect to said substrate.
4. The rail clamp circuit of claim 3 wherein said MIGFET has electrically isolated gate electrode regions on opposite sides of said vertical channel forming said first gate and said second gate.
5. The rail clamp circuit of claim 1 wherein said MIGFET is characterized as being an N-channel MIGFET and said ESD event detector adjusts said threshold voltage by lowering said threshold voltage.
6. The rail clamp circuit of claim 1 wherein said MIGFET is characterized as being an P-channel MIGFET and said ESD event detector adjusts said threshold voltage by raising said threshold voltage.
7. An integrated circuit comprising:
a first power supply voltage rail;
a second power supply voltage rail;
a trigger signal rail;
a VT signal rail;
a plurality of first input/output cells located adjacent to said first and second power supply voltage rails and each having a multiple independent gate field effect transistor (MIGFET) having a source-drain path coupled between said first and second power supply voltage rails, and having first and second gates respectively coupled to said trigger signal rail and said VT signal rail; and
an ESD event detector circuit coupled between said first and second power supply voltage rails, and having first and second output terminals respectively coupled to said trigger signal rail and to said VT signal rail, wherein in response to an electrostatic discharge (ESD) event between said first and second power supply voltage rails, said ESD event detector circuit provides a voltage to said VT signal rail to adjust a threshold voltage of said MIGFET of each of said plurality of first input/output cells while providing a voltage to said trigger signal rail to make said MIGFET conductive with relatively high conductivity.
8. The integrated circuit of claim 7 wherein each of said plurality of first input/output cells comprises a bonding pad.
9. The integrated circuit of claim 8 wherein each of said plurality of first input/output cells further comprises:
a first diode coupled between said bonding pad and said first power supply voltage rail; and
a second diode coupled between said second power supply voltage rail and said bonding pad.
10. The integrated circuit of claim 7 further comprising at least one second input/output cell comprising said ESD event detector circuit.
11. The integrated circuit of claim 10 further comprising a plurality of second input/output cells each comprising an ESD event detector circuit.
12. The integrated circuit of claim 11 wherein said plurality of second input/output cells is interspersed with said plurality of first input/output cells.
13. The integrated circuit of claim 12 wherein said plurality of first input/output cells and said plurality of second input/output cells occur in the ratio of about five to one.
14. The integrated circuit of claim 7 wherein said trigger signal rail is narrower than either said first power supply voltage rail or said second power supply voltage rail.
15. The integrated circuit of claim 7 wherein VT signal rail is narrower than either said first power supply voltage rail or said second power supply voltage rail.
16. A method of protecting an integrated circuit from an electrostatic discharge (ESD) event, comprising the steps of:
coupling a multiple independent gate field effect transistor (MIGFET) between first and second power supply voltage rails;
during normal operation, biasing a first gate of said MIGFET to select a relatively low leakage and biasing a second gate of said MIGFET to make said MIGFET nonconductive with said relatively low leakage; and
during the ESD event, biasing said first gate of said MIGFET to select a relatively high conductivity and biasing said second gate of said MIGFET to make said MIGFET conductive with said relatively high conductivity.
17. The method of claim 16 wherein said step of biasing said first gate of said MIGFET during the ESD event comprises the steps of:
detecting the ESD event; and
triggering said MIGFET to be conductive with said relatively high conductivity in response to said step of detecting.
18. The method of claim 17 wherein said step of triggering said MIGFET comprises the step of:
providing a trigger signal to said first gate of said MIGFET in response to said step of detecting.
19. The method of claim 16 wherein said step of coupling said MIGFET between said first and second power supply voltage rails comprises the step of coupling an N-channel MIGFET between said first and second power supply voltage rails, and said step of biasing said first gate of said MIGFET during the ESD event to select said relatively high conductivity comprises the step of lowering a threshold voltage of said N-channel MIGFET.
20. The method of claim 16 wherein said step of coupling said MIGFET between said first and second power supply voltage rails comprises the step of coupling a P-channel MIGFET between said first and second power supply voltage rails, and said step of biasing said first gate of said MIGFET during the ESD event to select said relatively high conductivity comprises the step of raising a threshold voltage of said P-channel MIGFET.