Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types
View Patent ↗A semiconductor fabrication process includes forming polysilicon nanocrystals on a tunnel oxide overlying a first region of a substrate. A second dielectric is deposited overlying the first region and a second region. Without providing any protective layer overlying the second dielectric in the first region, an additional thermal oxidation step is performed without oxidizing the nanocrystals. A gate electrode film is then deposited over the second dielectric and patterned to form first and second gate electrodes. The second dielectric may be an annealed, CVD oxide. The additional thermal oxidation may include forming by dry oxidation a third dielectric overlying a third region of the semiconductor substrate. The dry oxidation produces a interfacial silicon oxide underlying the second dielectric in the second region. An upper surface of a fourth region of the substrate may then be exposed and a fourth dielectric formed on the upper surface in the fourth region.
1. A semiconductor fabrication process, comprising:
forming a tunnel dielectric over first and second regions of a semiconductor substrate;
forming a charge storage element overlying the tunnel dielectric;
removing portions of the tunnel dielectric and the charge storage element overlying the second region;
forming a second dielectric overlying the first and second regions;
forming a conductive gate electrode layer overlying the second dielectric;
patterning the conductive gate electrode layer to form a first gate electrode overlying the first region and a second gate electrode overlying the second region;
forming first source/drain regions aligned to the first gate electrode in the first region and second source/drain regions aligned to the second gate electrode in the second region to form a thin film storage device in the first region and a high voltage transistor in the second region, wherein the second dielectric serves as a gate dielectric for the high voltage device and a control oxide for the thin film storage device.
2. The method of claim 1 , wherein forming the tunnel dielectric comprises thermally forming a silicon dioxide film having a thickness of approximately 3-7 nm.
3. The method of claim 2 , wherein forming the second dielectric comprises depositing a silicon oxide film by reacting an oxygen bearing species and a silicon bearing species in a CVD reactor chamber and thereafter annealing the silicon oxide film.
4. The method of claim 3 wherein a thickness of the second dielectric is in the range of approximately 5 to 15 nm.
5. The method of claim 1 , wherein forming the charge storage element comprises forming a plurality of silicon nanocrystals.
6. The method of claim 1 , wherein the semiconductor substrate includes a third region and wherein forming the second dielectric includes forming the second dielectric over the third region and wherein the method further comprises:
removing the second dielectric overlying the third region;
forming a third dielectric overlying the third region; and
forming a third transistor in the third region, the third transistors including a third gate electrode overlying the third gate dielectric and third source/drain regions wherein the third transistor uses the third dielectric.
7. The method of claim 6 , wherein forming the third dielectric comprises thermally forming a silicon dioxide film in a dry, oxygen bearing ambient.
8. The method of claim 7 , wherein the semiconductor substrate includes a fourth region and wherein the method further comprises, following forming the third dielectric, exposing an upper surface of the fourth region and forming a fourth dielectric overlying the fourth region.
9. The method of claim 1 , wherein the semiconductor substrate includes a third region and wherein forming the second dielectric includes forming the second dielectric over the third region and wherein the method further comprises thinning the portion of the second dielectric overlying the third region to form a third dielectric.
10. The method of claim 9 , wherein thinning the third dielectric comprises exposing the portion of the second dielectric overlying the third region to a process selected from the group consisting of a very dilute HF etch to a buffered oxide etch.
11. The method of claim 10 , further comprising, after forming the third dielectric, performing a dry oxidation process to form an interfacial oxide underlying the third dielectric in the third region and underlying the second dielectric in the second region.
12. A semiconductor fabrication process, comprising:
forming a plurality of silicon nanocrystals on a tunnel oxide selectively overlying a first region of a semiconductor substrate;
depositing a shared dielectric overlying the first region and a second region of the semiconductor substrate;
without providing any protective layer overlying the shared dielectric in the first region, performing at least one additional thermal oxidation step, wherein the presence of the shared dielectric overlying the silicon nanocrystals substantially prevents the additional thermal oxidation step from oxidizing the nanocrystals; and
depositing a conductive gate electrode film overlying the shared dielectric and patterning the gate electrode film to form a first gate electrode overlying the first region and a second gate electrode overlying the second region.
13. The method of claim 12 , wherein depositing the shared dielectric comprises chemically vapor depositing a silicon oxide dielectric and, thereafter, annealing the deposited dielectric.
14. The method of claim 13 , wherein performing the at least one additional thermal oxidation includes performing a dry oxidation process to form a third dielectric overlying a third region of the semiconductor substrate.
15. The method of claim 14 , wherein the dry oxidation process produces a interfacial silicon oxide film underlying the shared dielectric in the second region.
16. The method of claim 15 , further comprising exposing an upper surface of a fourth region of the semiconductor substrate and thermally forming a fourth dielectric on the upper surface in the fourth region.
17. The method of claim 16 , wherein a thickness of the shared dielectric is greater than a thickness of the third dielectric and wherein a thickness of the third dielectric is greater than a thickness of the fourth dielectric.