Method of testing for power and ground continuity of a semiconductor device
View Patent ↗A method of testing for power and ground continuity of a semiconductor device having Input and Output (IO) pins and at least a pair of power and ground pins includes identifying the power and ground pins of the device. A victim pin is selected from the IO pins of the device for each pair of the power and ground pins, and an aggressor pin for each victim pin is selected from the remaining IO pins. The aggressor pins are toggled between a high state and a low state. A level of switching noise on each victim pin is measured, and the measured levels of switching noise are compared with predetermined data to determine power and ground continuity of the device.
1. A method of testing for power and ground continuity of a semiconductor device, the device having a plurality of Input and Output (IO) pins and at least a pair of power and ground pins, the method comprising:
identifying the power and ground pins of the device;
selecting a victim pin from the IO pins of the device for each of the power and ground pins;
selecting at least one aggressor pin for each victim pin from the remaining IO pins;
toggling the aggressor pins between a first state and a second state;
measuring a level of switching noise on each victim pin; and
comparing the measured levels of switching noise with predetermined data to determine power and ground continuity of the device.
2. The method of continuity testing of claim 1 , wherein a plurality of aggressor pins is selected for each victim pin.
3. The method of continuity testing of claim 2 , wherein the aggressor pins are toggled substantially simultaneously.
4. The method of continuity testing of continuity testing of claim 1 , wherein the level of switching noise on each victim pin is amplified by the toggling of the aggressor pins.
5. The method of continuity testing of claim 1 , wherein the level of switching noise on each victim pin is measured when the at least one aggressor pin is toggled from a high state to a low state.
6. The method of continuity testing of claim 5 , wherein a maximum level of switching noise on each victim pin is measured.
7. The method of continuity testing of claim 1 , wherein IO pins adjacent to the power and ground pins are selected as the respective victim pins.
8. The method of continuity testing of claim 7 , wherein the power and ground pins are paired and one victim pin is selected for each power and ground pin pair.
9. The method of continuity testing of claim 1 , wherein the victim pin is held at a fixed state.
10. The method of continuity testing of claim 1 , wherein the predetermined data comprises switching noise measurements from at least one known good semiconductor device.
11. The method of continuity testing of claim 1 , wherein the victim and aggressor pins are terminated with a terminating resistor.
12. The method of continuity testing of claim 11 , wherein the terminating resistor has a resistance that matches a trace impedance of a load board on which the device is tested.
13. A method of testing for power and ground continuity of a semiconductor device, the device having a plurality of Input and Output (IO) pins and at least a pair of power and ground pins, the method comprising:
identifying the power and ground pins of the device;
selecting victim pins from the IO pins of the device for each of the power and ground pins;
selecting at least one aggressor pin from the remaining IO pins;
toggling the at least one aggressor pin between a high state and a low state;
measuring a level of switching noise on the victim pins;
comparing the measured level of switching noise with predetermined test data to determine continuity of the power and ground pins; and
repeating the victim pin selecting step, the agressor pin selecting step, the toggling step, the measuring step and the comparing step for each power and ground pin.
14. The method of continuity testing of claim 13 , wherein a plurality of aggressor pins is selected.
15. The method of continuity testing of claim 14 , wherein the aggressor pins are toggled substantially simultaneously.
16. The method of continuity testing of claim 15 , wherein the level of switching noise on the victim pin is measured when the aggressor pins are toggled from a high state to a low state.
17. The method of continuity testing of claim 13 , wherein the respective victim pins are adjacent their corresponding ground and power pins.
18. The method of continuity testing of claim 13 , wherein the predetermined data comprises switching noise measurements from at least one known good semiconductor device.
19. The method of continuity testing of claim 13 , wherein the power and ground pins are paired and a victim pins are selected for each power and ground pin pair.
20. A computer readable medium tangibly embodying a program of instructions for power and ground continuity testing of a semiconductor device having a plurality of Input and Output (IO) pins and at least a pair of power and ground pins, the program to be stored in a memory and executed by a processor, the program comprising:
instructions to identify the power and ground pins of the device;
instructions to select a victim pin from the IO pins of the device for each of the power and ground pins;
instructions to select at least one aggressor pin from the remaining IO pins for each victim pin;
instructions to toggle the aggressor pins between a high state and a low state;
instructions to measure a level of switching noise on each victim pin; and
instructions to compare the measured levels of switching noise with predetermined data to determine power and ground continuity of the device.