Method and system for simultaneous reads of multiple arrays
View Patent ↗A method and system for simultaneously reading data from multiple indexed arrays, where each indexed array includes one or more memory locations and is coupled to a multiplexing circuit. Each multiplexing circuit includes one or more multiplexers and is driven by a set of input selector signals. The method includes enabling each multiplexing circuit with a distinct combination of the set of input selector signals. The distinct combinations of the set of input selector signals cause each input selector signal to drive a comparable number of multiplexers. Each multiplexing circuit selects a memory location from the coupled indexed array. Further, the method includes reading the data at the selected memory locations through the output of each multiplexing circuit.
1. A method for simultaneously reading data from a plurality of indexed arrays, each of the plurality of indexed arrays comprising one or more memory locations, each indexed array of the plurality of indexed arrays being coupled to a multiplexing circuit, each multiplexing circuit comprising one or more multiplexers, each multiplexing circuit being driven by a set of input selector signals, the method comprising:
enabling each multiplexing circuit with a distinct combination of the set of input selector signals, wherein each multiplexing circuit selects a memory location from the coupled indexed array; and
reading the data at the selected memory locations through an output of each multiplexing circuit, wherein the distinct combinations of the set of input selector signals are generated by interchanging positions of the set of input selector signals for each indexed array of the plurality of indexed arrays.
2. The method for simultaneously reading data from the plurality of indexed arrays of claim 1 , wherein each input selector signal of the set of input selector signals drives an equal number of multiplexers from the one or more multiplexers.
3. The method for simultaneously reading data from the plurality of indexed arrays of claim 2 , further comprising driving the set of input selector signals with a plurality of buffer elements, wherein the plurality of buffer elements are distributed equally among the set of input selector signals.
4. The method for simultaneously reading data from the plurality of indexed arrays of claim 1 , further comprising selecting a memory location of the one or more memory locations of each indexed array of the plurality of indexed arrays based on the distinct combinations of the set of input selector signals applied to each multiplexing circuit.
5. The method for simultaneously reading data from the plurality of indexed arrays of claim 1 , wherein cardinality of the set of input selector signals is based on the number of the one or more memory locations in each indexed array of the plurality of indexed arrays.
6. The method for simultaneously reading data from the plurality of indexed arrays of claim 1 , further comprising rearranging the indexing of the plurality of indexed arrays based on the distinct combinations of the set of input selector signals.
7. A memory accessing circuit, comprising:
a plurality of buffer elements that drive a set of input selector signals, wherein the buffer elements are distributed in a pre-defined manner among the set of input selector signals; and
one or more multiplexing circuits driven by the set of input selector signals, wherein each multiplexing circuit is connected to one or more memory locations of an indexed array from a plurality of indexed arrays, wherein the one or more memory locations of the plurality of indexed arrays are used for storing data, wherein the data is selected from the one or more memory locations based on distinct combinations of the set of input selector signals, and wherein indexing of the one or more memory locations of each indexed array of the plurality of indexed arrays is rearranged based on the combinations of the set of input selector signals.
8. The memory accessing circuit of claim 7 , wherein the pre-defined manner comprises organizing the buffer elements equally among the set of input selector signals.