Granted Patent B1

US 7,102,365 · App. 11/097,593 · Granted Sep 5, 2006

Abstract

Claims (44)

1. A circuit for sensing a current, the circuit comprising:

a first switched capacitor network comprising a first set of capacitors, said first switched capacitor network having an output and having an input configured to sample each of first, second, and third reference potentials across a different capacitor of said first set of capacitors during each of two phases, said first and second reference potentials indicating the current;

a second switched capacitor network comprising a second set of capacitors exclusive of said first set of capacitors, said second switched capacitor network having a first terminal coupled to said input of said amplifier and having a second terminal coupled to said output of said amplifier, said second switched capacitor network configured to cancel an offset voltage at said input of said amplifier; and

an amplifier having an output and having an input coupled to said output of said first switched capacitor network, said amplifier configured to produce first and second amplified potentials at said output of said amplifier based on said first and second reference potentials.

2. A circuit according to claim 1 , wherein said input of said amplifier comprises a first input and a second input; and

wherein said first switched capacitor network comprises:

a first switchable capacitor having a first electrode coupled to said first input of said amplifier and a second electrode configured to couple to a third reference potential in a first phase and to said first reference potential in a second phase;

a second switchable capacitor having a first electrode coupled to said first input of said amplifier and having a second electrode configured to couple to said second reference potential in said first phase and to said third reference potential in said second phase;

a third switchable capacitor having a first electrode coupled to said second input of said amplifier and having a second electrode configured to couple to said third reference potential in said first phase and to said second reference potential in said second phase; and

a fourth switchable capacitor having a first electrode coupled to said second input of said amplifier and having a second electrode configured to couple to said first reference potential in said first phase and to said third reference potential in said second phase.

3. A circuit according to claim 2 , wherein said first switched capacitor network comprises:

a first switch having a first terminal coupled to said second electrode of said first switchable capacitor and having a second terminal coupled to said first reference potential, said fit switch configured to couple said first terminal of said first switch with said second terminal of said first switch in said second phase; and

a second switch having a first terminal coupled to said second electrode of said first switchable capacitor and having a second terminal coupled to said third reference potential, said second switch configured to couple said first terminal of said second switch with said second terminal of said second switch in said first phase;

wherein said second switchable capacitor comprises:

a third switch having a first terminal coupled to said second electrode of said second switchable capacitor and having a second terminal coupled to said second reference potential, said third switch configured to couple said first terminal of said third switch with said second terminal of said third switch in said first phase; and

a fourth switch having a first terminal coupled to said second electrode of said second switchable capacitor and having a second terminal coupled to said third reference potential, said fourth switch configured to couple said first terminal of said fourth switch with said second terminal of said fourth switch in said second phase;

wherein said third switchable capacitor comprises:

a fifth switch having a first terminal coupled to said second electrode of said third switchable capacitor and having a second terminal coupled to said second reference potential, said fifth switch configured to couple said first terminal of said fifth switch to said second terminal of said fifth switch in said second phase; and

a sixth switch having a first terminal coupled to said second electrode of said third switchable capacitor and having a second terminal coupled to said third reference potential, said sixth switch configured to couple said first terminal of said sixth switch to said second terminal of said sixth switch in said first phase; and

wherein said fourth switchable capacitor comprises:

a seventh switch having a first terminal coupled to said second electrode of said fourth switchable capacitor and having a second terminal coupled to said first reference potential, said seventh switch configured to couple said first terminal of said seventh switch to said second terminal of said seventh switch in said first phase; and

an eighth switch having a first terminal coupled to said second electrode of said fourth switchable capacitor and having a second terminal coupled to said third reference potential, said eighth switch configured to couple said first terminal of said eighth switch to said second terminal of said eighth switch in said second phase.

4. A circuit according to claim 1 , wherein said input of said amplifier comprises first and second inputs, and said output of said amplifier comprises first and second outputs; and

wherein said second switched capacitor network comprises:

a first switchable capacitor having a first electrode coupled to said first input of said amplifier and having a second electrode coupled to a third reference potential in a first phase and to said first output of said amplifier in a second phase; and

a second switchable capacitor having a first electrode coupled to said second input of said amplifier and having a second electrode coupled to said third reference potential in said first phase and to said second output of said amplifier in said second phase.

5. A circuit according to claim 4 , wherein said first switched capacitor network comprises:

a first switch having a first terminal coupled to said second electrode of said first switchable capacitor and having a second terminal coupled to said third reference potential, said first switch configured to couple said first terminal of said first switch with said second terminal of said first switch in said first phase; and

a second switch having a first terminal coupled to said second electrode of said first switchable capacitor and having a second terminal coupled to said first output of said amplifier, said second switch configured to couple said first terminal of said second switch to said second terminal of said second switch in said second phase; and

wherein said second switchable capacitor comprises:

a third switch having a first terminal coupled to said second electrode of said second switchable capacitor and having a second terminal coupled to said third reference potential, said third switch configured to couple said first terminal of said third switch with said second terminal of said third switch in said first phase; and

a fourth switch having a first terminal coupled to said second electrode of said second switchable capacitor and having a second terminal coupled to said second output of said amplifier, said second switch configured to couple said first terminal of said fourth switch to said second terminal of said fourth switch in said second phase.

6. A circuit according to claim 1 further comprising a Common Mode FeedBack circuit (CMFB) coupled to said output of said amplifier.

7. A circuit for sensing a current, the circuit comprising:

a first switched capacitor network comprising a first set of capacitors, said first switched capacitor network having an output and configured to sample first, second, and third reference potentials across a different capacitor of said first set of capacitors during each of two phases, said first and second reference potentials indicating the current;

an amplifier having an input coupled to said output of said first switched capacitor network and having an output, said amplifier configured to produce first and second amplified potentials from said first and second reference potentials;

a second switched capacitor network comprising a second set of capacitors exclusive of said first set of capacitors, said second switched capacitor network having an input coupled to said output of said amplifier and having an output coupled to said input of said amplifier, said second switched capacitor network configured to produce third and fourth amplified potentials from said first and second amplified potentials via said amplifier at said output of said amplifier; and

an S/H stage having an input coupled to said output of said amplifier and configured to produce a sampled potential from said third and fourth amplified potentials and hold said sampled amplified potential for a pre-determined time period.

8. A circuit according to claim 7 , further comprising:

an amplifier having an input coupled to said first switched capacitor network and having an output; and

a third switched capacitor network having a first terminal coupled to said input of said amplifier and having a second terminal coupled to said output of said amplifier, said third switched capacitor network configured to cancel a first offset voltage at said input of said amplifier during a first phase; and

wherein said first switched capacitor network is further configured to sample said first and second reference potentials during a second phase, and said amplifier is configured to scale said first and second reference potentials to produce said first and second amplified potentials at said output.

9. A circuit according to claim 8 further comprising a fourth switched capacitor network having a first terminal coupled to said output of said amplifier and having a second terminal coupled to said input of said amplifier, said fourth switched capacitor network configured to cancel a second offset voltage at said input of said second switched capacitor network during a third phase; and

wherein said second switched capacitor network is further configured to produce said third and fourth amplified potentials during a fourth phase.

Assignments (17)