Hybrid-FET and its application as SRAM
View Patent ↗A semiconductor device ( 51 ) is provided herein. The semiconductor device comprises (a) a substrate ( 57 ), a semiconductor layer ( 53 ) disposed on said substrate and comprising a horizontal region ( 54 ) and a fin which extends above, and is disposed adjacent to, said horizontal region, and (c) at least one channel region ( 63 ) defined in said fin and in said horizontal region.
1. A semiconductor device, comprising:
a substrate;
a semiconductor layer disposed on said substrate and comprising an essentially planar region;
a fin, disposed on said planar region;
at least one channel region defined in said fin and in said planar region; and
a gate extending across said fin and said planar region; wherein said fin comprises at least one source region disposed on a first side of said gate, and at least one drain region disposed on a second side of said gate, and wherein said at least one source region or said at least one drain region is a continuous region which extends over said fin and also extends over said planar region.
2. The semiconductor device of claim 1 , wherein said at least one source region is a continuous region which extends over said fin and also extends over said planar region.
3. The semiconductor device of claim 1 , wherein said at least one drain region is a continuous region which extends over said fin and also extends over said planar region.
4. The semiconductor device of claim 1 , wherein said planar region comprises at least one source region disposed on a first side of said gate, and at least one drain region disposed on a second side of said gate.
5. The semiconductor device of claim 1 , wherein a first end of said fin terminates in a first semiconductor wall, and wherein said at least one source region extends over said first wall.
6. The semiconductor device of claim 1 , wherein said device is an SRAM cell.
7. The semiconductor device of claim 1 , wherein said device is a FINFET.
8. The semiconductor device of claim 1 , further comprising a dielectric layer, and wherein said dielectric layer is disposed between said substrate and said semiconductor layer.
9. The semiconductor device of claim 1 , wherein said fin is in physical contact with said planar region.
10. The semiconductor device of claim 1 , wherein said fin is essentially perpendicular to said planar region.
11. The semiconductor device of claim 1 , wherein said fin is capped with a nitride layer.
12. The semiconductor device of claim 11 , further comprising a dielectric layer disposed between said fin and said nitride layer.
13. The semiconductor device of claim 1 , wherein said fin and said planar region form a unitary structure.
14. The semiconductor device of claim 1 , wherein said substrate is a semiconductor substrate.
15. The semiconductor device of claim 1 , wherein said substrate, said gate and said semiconductor layer comprise silicon.
16. The semiconductor device of claim 1 , wherein said gate comprises a material selected from the group consisting of tungsten, titanium, titanium nitride, tantalum silicon nitride, cobalt silicide, nickel silicide, germanium, and silicon germanium.
17. The semiconductor device of claim 1 , wherein said substrate has a layer of SiGe or Ge therein.
18. The semiconductor device of claim 1 , wherein the width of said fin is greater than the height of said planar region.
19. The semiconductor device of claim 1 , wherein the length of said gate is greater than the width of said fin, and wherein the thickness of said gate is greater than the height of the planar region.
20. The semiconductor device of claim 1 , wherein the length of said gate is greater than the height of said planar region.