Semiconductor structure with reduced gate doping and methods for forming thereof
View Patent ↗A semiconductor structure includes a substrate having a memory region and a logic region. A first p-type device is formed in the memory region and a second p-type device is formed in the logic region. At least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device. The semiconductor gates of the first and second p-type devices each have a non-zero p-type dopant concentration.
1. A method for forming a semiconductor structure comprising:
providing a substrate having a memory region and a logic region; and forming a first p-type device in the memory region and a second p-type device in the logic region, wherein at least a portion of a semiconductor gate of the first p-type device has a lower p-type dopant concentration than at least a portion of a semiconductor gate of the second p-type device, the semiconductor gates of the first and second p-type devices each having a non-zero p-type dopant concentration, wherein forming further comprises:
performing a diffusion-reducing implant in a semiconductor gate layer corresponding to the first p-type device and the second p-type device, and wherein the memory region further comprises a first device region having p-type devices and a second device region having n-type devices, and wherein the diffusion-reducing implant is performed in the semiconductor gate layer in only the first device region of the memory region, prior to forming the semiconductor gates of the first and second p-type devices.
2. The method of claim 1 , wherein forming further comprises:
performing a first p-type implant into a portion of the semiconductor gate layer used to form the semiconductor gate of the first p-type device;
performing a second p-type implant into a portion of the semiconductor gate layer used to form the semiconductor gate of the second p-type device, wherein the first p-type implant uses a lower p-type dose than the second p-type implant; and
patterning the semiconductor gate layer to form the semiconductor gates of the first and second p-type devices.
3. The method of claim 2 , wherein the first p-type implant is a blanket implant into the semiconductor gate layer.
4. The method of claim 1 , wherein the diffusion-reducing implant is performed using a species selected from a group consisting of nitrogen, carbon, and germanium.
5. The method of claim 1 , wherein forming further comprises:
forming a source/drain region in the substrate adjacent each side of the semiconductor gate of the first p-type device, the source/drain regions extending under the semiconductor gate of the first p-type device; and
performing an anneal, wherein the diffusion-reducing implant is performed into the semiconductor gate of the first p-type device prior to the anneal.
6. The method of claim 1 , wherein the diffusion-reducing implant is selectively implanted into a portion of the semiconductor gate layer that is used to form the semiconductor gate of the first p-type device.
7. The method of claim 1 , wherein forming further comprises:
forming a hardmask layer over the semiconductor gate layer; and
forming the semiconductor gates of the first and second p-type devices; and
performing a source/drain implant to form source/drain regions adjacent the semiconductor gate of the first p-type device, wherein a portion of the hardmask layer remains over the semiconductor gate of the first p-type device during the source/drain implant.
8. The method of claim 1 , wherein forming further comprises:
depositing an in-situ p-type doped semiconductor gate layer over the substrate; and
patterning the in-situ p-type doped semiconductor gate layer to form the semiconductor gates of the first and second p-type devices.
9. A method for forming a semiconductor structure comprising:
providing a substrate having a memory region and a logic region;
forming a gate dielectric layer over the substrate;
forming a semiconductor gate layer over the gate dielectric layer;
patterning the semiconductor gate layer to form a first semiconductor gate in the memory region and a second semiconductor gate in the logic region, wherein at least a portion of the first semiconductor gate has a lower dopant concentration of the first conductivity type than at least a portion of the second semiconductor gate;
performing a diffusion-reducing implant in the memory region, wherein the memory region further comprises a first device region having devices of the first conductivity type and a second device region having devices of a second conductivity type, and wherein the diffusion-reducing implant is performed in the semiconductor gate layer in only the first device region of the memory region, prior to forming the first and second semiconductor gates; and
forming source/drain regions in the substrate, adjacent the first semiconductor gate.
10. The method of claim 9 , further comprising:
performing a first implant having the first conductivity type into the semiconductor gate layer.
11. The method of claim 10 , wherein the first implant is performed as a blanket implant.
12. The method of claim 10 , further comprising:
performing a second implant having the first conductivity type into the semiconductor gate layer in the logic region while masking the semiconductor gate layer in the memory region, wherein the second implant is performed either prior to or after the first implant.
13. The method of claim 10 , wherein the memory region further comprises a first device region having devices of the first conductivity type and a second device region having devices of a second conductivity type, and wherein the first implant is performed in only the first device region of the memory region.
14. The method of claim 9 , wherein the diffusion-reducing implant comprises a species selected from a group consisting of nitrogen, carbon, and germanium.
15. The method of claim 9 , wherein the diffusion-reducing implant is performed into the first semiconductor gate.
16. The method of claim 15 , wherein the diffusion-reducing implant comprises a species selected from a group consisting of nitrogen, carbon, and germanium.
17. The process of claim 9 , further comprising:
forming a hardmask layer over the semiconductor gate layer, wherein a portion of the hardmask layer remains over the first semiconductor gate during the forming of the source/drain regions.
18. The method of claim 9 , wherein the first conductivity type is p-type.
19. The method of claim 9 , wherein forming the semiconductor gate layer comprises depositing an in-situ doped layer having a dopant concentration of the first conductivity type.