IP Library Granted Patent US 6,870,219
Granted Patent B2
US 6,870,219 · App. 10/209,816 · Granted Mar 22, 2005

Field effect transistor and method of manufacturing same

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Quick Facts
Patent No.
US 6,870,219
App. No.
10/209,816
Granted
Mar 22, 2005
Kind
B2
Abstract

A field effect transistor includes a drain region ( 12 ) having a first portion ( 18 ) and a second portion ( 20 ), with the second portion being more lightly doped than the first portion. A channel region ( 14 ) is adjacent to the second portion and a drain electrode ( 24 ) overlies the drain region. A gate electrode ( 16 ) overlies the channel region. A shield structure ( 30 ) overlies the drain region and has a first section ( 32 ) at a first distance ( 33 ) from a semiconductor substrate ( 10 ) and a second section ( 34 ) at a second distance ( 35 ) from the semiconductor substrate, the second distance being greater than the first distance. In a particular embodiment the FET includes a shield structure wherein the first and second sections are physically separate. The location of these shield sections may be varied within the FET, and the potential of each section may be independently controlled.

Claims (79)

1. A field effect transistor comprising:

a semiconductor substrate having a surface;

a drain region in the semiconductor substrate and having a first portion and a second portion more lightly doped than the first portion;

a channel region in the semiconductor substrate and adjacent to the second portion of the drain region;

a gate electrode overlying the channel region and located over the surface of the semiconductor substrate;

a drain electrode overlying the first portion of the drain region and located over the surface of the semiconductor substrate; and

an electrically conductive shield structure overlying the second portion of the drain region,

wherein:

the electrically conductive shield structure comprises:

a first section at a first distance from the semiconductor substrate; and

a second section at a second distance from the semiconductor substrate and at a third distance from the gate electrode;

at least a portion of the electrically conductive shield structure overlies at least a portion of the gate electrode;

the first section and the second section are electrically biased;

the second distance is greater than the first distance;

the third distance is greater than the first distance; and

the drain electrode is closer to the second section of the electrically conductive shield structure than to the first section of the electrically conductive shield structure.

2. A field effect transistor comprising:

a semiconductor substrate;

a drain region in the semiconductor substrate and having a first portion and a second portion more lightly doped than the first portion;

a channel region in the semiconductor substrate and adjacent to the second portion of the drain region;

a gate electrode overlying the channel region;

a drain electrode overlying the first portion of the drain region; and

an electrically conductive shield structure overlying the second portion of the drain region, having a first section at a first distance from the semiconductor substrate, and having a second section at a second distance from the semiconductor substrate, the second distance greater than the first distance,

wherein:

the first and second sections of the electrically conductive shield structure are separately biased;

the first section of the electrically conductive shield structure is electrically coupled to a predetermined potential approximately equal to a threshold voltage for the field effect transistor; and

the second section of the electrically conductive shield structure is electrically coupled to a ground potential.

3. A field effect transistor comprising:

a semiconductor substrate having a surface;

a drain region in the semiconductor substrate and having a first portion and a second portion more lightly doped than the first portion;

a channel region in the semiconductor substrate and adjacent to the second portion of the drain region;

a gate electrode over the surface of the semiconductor substrate and over the channel region;

a drain electrode over the surface of the semiconductor substrate and over the first portion of the drain region; and

an electrically conductive shield structure having a first section and a second section,

wherein:

the first section and the second section of the electrically conductive shield structure are electrically biased;

the first section of the electrically conductive shield structure is over the second portion of the drain region;

the first section of the electrically conductive shield structure is at a first distance from the surface of the semiconductor substrate;

the second section of the electrically conductive shield structure is over the gate electrode;

the second section of the electrically conductive shield structure is at a second distance from the surface of the semiconductor substrate and at a third distance from the gate electrode;

the first and second distances are measured along paths perpendicular to the surface of the semiconductor substrate;

the first distance is less than the second distance;

the third distance is greater than the first distance;

the third distance is less than the second distance; and

the drain electrode is closer to the second section of the electrically conductive shield structure than the first section of the electrically conductive shield structure.

4. A field effect transistor comprising:

a semiconductor substrate having a surface;

a drain region in the semiconductor substrate and having a first portion and a second portion more lightly doped than the first portion;

a channel region in the semiconductor substrate and adjacent to the second portion of the drain region;

a gate electrode over the surface of the semiconductor substrate and over the channel region;

a drain electrode over the surface of the semiconductor substrate and over the first portion of the drain region; and

an electrically conductive shield structure having a first section and a second section,

wherein:

the first section and the second section of the electrically conductive shield structure are electrically biased;

the first section of the electrically conductive shield structure is over the second portion of the drain region;

the first section of the electrically conductive shield structure is at a first distance from the surface of the semiconductor substrate;

the second section of the electrically conductive shield structure is over the gate electrode;

the second section of the electrically conductive shield structure is at a second distance from the surface of the semiconductor substrate and at a third distance from the gate electrode;

the first and second distances are measured along paths perpendicular to the surface of the semiconductor substrate;

the first distance is less than the second distance;

the third distance is greater than the first distance;

the third distance is less than the second distance;

the second section of the electrically conductive shield structure is also over the first section of the electrically conductive shield structure; and

the drain electrode is closer to the second section of the electrically conductive shield structure than the first section of the electrically conductive shield structure.

5. A field effect transistor comprising:

a semiconductor substrate having a surface;

a drain region in the semiconductor substrate and having a first portion and a second portion more lightly doped than the first portion;

a channel region in the semiconductor substrate and adjacent to the second portion of the drain region;

a gate electrode over the surface of the semiconductor substrate and over the channel region;

a drain electrode over the surface of the semiconductor substrate and over the first portion of the drain region; and

an electrically conductive shield structure having a first section and a second section,

wherein:

the first section of the electrically conductive shield structure is over the second portion of the drain region;

the first section of the electrically conductive shield structure is t a first distance from the surface of the semiconductor substrate;

the second section of the electrically conductive shield structure is over the gate electrode;

the second section of the electrically conductive shield structure is at a second distance from the surface of the semiconductor substrate;

the first distance is less than the second distance;

the first section of the electrically conductive shield structure is electrically coupled to a predetermined potential approximately equal to a threshold voltage for the field effect transistor; and

the second section of the electrically conductive shield structure is electrically coupled to a ground potential.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2004
From: MOTOROLA, INC
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 015360/0718 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2002
From: BRECH, HELMUT
To: MOTOROLA, INC.
Reel/Frame 013163/0215 →