IP Library Granted Patent US 7,361,987
Granted Patent B2
US 7,361,987 · App. 11/148,691 · Granted Apr 22, 2008

Circuit device with at least partial packaging and method for forming

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Quick Facts
Patent No.
US 7,361,987
App. No.
11/148,691
Granted
Apr 22, 2008
Kind
B2
Abstract

A circuit device ( 15 ) is placed within an opening of a conductive layer ( 10 ) which is then partially encapsulated with an encapsulant ( 24 ) so that the active surface of the circuit device ( 15 ) is coplanar with the conductive layer ( 10 ). At least a portion of the conductive layer ( 10 ) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device ( 115 ) may be placed on a conductive layer ( 100 ) such that an active surface of circuit device ( 115 ) is between conductive layer ( 100 ) and an opposite surface of circuit device ( 115 ). The conductive layer ( 100 ) has at least one opening ( 128 ) to expose the active surface of circuit device ( 115 ). The encapsulant ( 24, 126, 326 ) may be electrically conductive or electrically non-conductive.

Claims (48)

1. A device with at least partial packaging, comprising:

a circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry;

an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening, wherein:

the at least one opening at least partially surrounds the circuit device,

the first surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and

the electrically conductive layer comprises a first reference voltage plane;

an electrical contact, electrically coupled to the first reference voltage plane, said electrical contact enabling electrical contact to be made to said first reference voltage plane; and

an encapsulant layer at least partially filling a gap within the at least one opening between the circuit device and the electrically conductive layer, wherein the encapsulant layer overlies at least a first portion of the second surface of the electrically conductive layer.

2. The device of claim 1 , wherein the encapsulant layer comprises an electrically conductive material.

3. The device of claim 1 , wherein the encapsulant layer overlies at least a portion of the second surface of the circuit device.

4. The device of claim 1 , further comprising a second circuit device in physical contact with a second portion of the second surface of the electrically conductive layer.

5. The device of claim 4 , wherein the second circuit device is selected from a group consisting of a passive device, an optical device, an active device, and a semiconductor device, an antennae, and a micro-electro-mechanical system (MEMS) device.

6. The device of claim 4 , wherein the encapsulant layer overlies at least a portion of the second circuit device.

7. The device of claim 1 , wherein the first reference voltage plane is electrically coupled to the circuit device.

8. A device with at least partial packaging, comprising:

a circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry;

an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening, wherein:

the at least one opening at least partially surrounds the circuit device,

the first surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and

the electrically conductive layer comprises a first reference voltage plane;

an electrical contact, electrically coupled to the first reference voltage plane, said electrical contact enabling electrical contact to be made to said first reference voltage plane; and

an encapsulant layer at least partially filling a gap within the at least one opening between the circuit device and the electrically conductive layer, wherein the encapsulant layer overlies at least a portion of the second surface of the circuit device.

9. A device with at least partial packaging, comprising:

a circuit device having a first surface and a second surface opposite the first surface, wherein the first surface comprises active circuitry;

an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening, wherein:

the at least one opening at least partially surrounds the circuit device,

the first surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and

the electrically conductive layer comprises a first reference voltage plane;

an electrical contact, electrically coupled to the first reference voltage plane, said electrical contact enabling electrical contact to be made to said first reference voltage plane;

an encapsulant layer at least partially filling a gap within the at least one opening between the circuit device and the electrically conductive layer; and

a plurality of circuit devices, wherein said circuit device is a first one of the plurality of circuit devices, wherein the electrically conductive layer comprises a plurality of openings, wherein each of the plurality of openings at least partially surrounds one of the plurality of circuit devices.

10. The device of claim 9 , wherein each of the plurality of circuit devices has a first surface comprising active circuitry and a second surface opposite the first surface, wherein the first surfaces of each of the plurality of the circuit devices is substantially coplanar with the first surface of the electrically conductive layer.

11. The device of claim 10 , wherein the encapsulant layer overlies at least a portion of the second surfaces of the plurality of circuit devices.

12. The device of claim 11 , wherein the encapsulant layer comprises an electrically conductive material.

13. A method for forming a device having at least partial packaging, comprising:

providing an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening;

attaching an adhesive layer to the electrically conductive layer;

placing a circuit device on the adhesive layer within the at least one opening, wherein an active surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and wherein the electrically conductive layer comprises a reference voltage plane;

providing an electrical contact electrically coupled to the reference voltage plane;

forming an encapsulant layer to at least partially fill a gap within the at least one opening between the circuit device and the electrically conductive layer; and

removing the adhesive layer after forming the encapsulant layer.

14. The method of claim 13 , wherein the adhesive layer comprises a tape.

15. A method for forming a device having at least partial packaging, comprising:

providing an electrically conductive layer having a first surface, a second surface opposite the first surface, and at least one opening;

attaching an adhesive layer to the electrically conductive layer;

placing a circuit device on the adhesive layer within the at least one opening, wherein an active surface of the circuit device is substantially coplanar with the first surface of the electrically conductive layer, and wherein the electrically conductive layer comprises a reference voltage plane;

providing an electrical contact electrically coupled to the reference voltage plane;

forming an encapsulant layer to at least partially fill a gap within the at least one opening between the circuit device and the electrically conductive layer, wherein forming the encapsulant layer comprises forming a mold compound overlying the circuit device and the second surface of the electrically conductive layer.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE LISTED CHANGE OF NAME SHOULD BE MERGER AND CHANGE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0180. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 12, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 041354/0148 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 040652/0180 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037518/0292 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0225 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0553 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037354/0719 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 030633/0424 →
SECURITY AGREEMENT Recorded May 13, 2010
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS COLLATERAL AGENT
Reel/Frame 024397/0001 →
SECURITY AGREEMENT Recorded Sep 24, 2008
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A.
Reel/Frame 021570/0449 →
SECURITY AGREEMENT Recorded Feb 2, 2007
From: FREESCALE SEMICONDUCTOR, INC.; FREESCALE ACQUISITION CORPORATION; FREESCALE ACQUISITION HOLDINGS CORP.; FREESCALE HOLDINGS (BERMUDA) III, LTD.
To: CITIBANK, N.A. AS COLLATERAL AGENT
Reel/Frame 018855/0129 →