Temperature based DRAM refresh
View Patent ↗A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.
1. An electronic system comprising:
a first integrated circuit die including:
an array of dynamic random access memory (DRAM) cells;
a temperature sensor;
refresh circuitry, the refresh circuitry for refreshing the DRAM cells of the array;
refresh determination circuitry operably coupled to the temperature sensor, the refresh determination circuitry for generating requests to initiate a refresh cycle to refresh the array based upon a measured temperature of the temperature sensor; and
an external output, the external output providing a refresh request indication externally from the first integrated circuit die, wherein the refresh request indication is indicative of a request to execute the refresh cycle of the array based upon the measured temperature of the temperature sensor; and
a second integrated circuit die including:
an input, the input coupled to receive the refresh request indication; and
control circuitry, wherein the control circuitry of the second integrated circuit die utilizes the received refresh request indication to initiate the refresh cycle of the array.
2. The electronic system of claim 1 wherein during a self refresh mode of operation, control circuitry of the first integrated circuit die initiates self refresh cycles of the array by the refresh circuitry.
3. The electronic system of claim 2 wherein during an active mode of operation, the first integrated circuit die provides the refresh request indication to indicate a request to execute a refresh cycle of the array, wherein the first integrated circuit die provides the refresh request indication to indicate a request to execute a refresh cycle of the array based upon a measured temperature of the temperature sensor.
4. The electronic system of claim 3 wherein during an active mode of operation, the second integrated circuit die provides data to the first integrated circuit die to be written in the array.
5. The electronic system of claim 1 wherein during a self refresh mode of operation, the first integrated circuit die does not provide the refresh request indication to request an execution of a refresh cycle.
6. The electronic system of claim 1 wherein the second integrated circuit die includes a programmable register, wherein the contents of the register are indicative of whether the control circuitry of the second integrated circuit die is responsive to the refresh request indication.
7. The electronic system of claim 1 wherein:
the external output includes a terminal of the first integrated circuit die and the refresh request indication includes an assertion of a signal provided by the terminal.
8. The electronic system of claim 1 further comprising:
a third integrated circuit die including:
a second array of dynamic random access memory (DRAM) cells;
a second temperature sensor;
refresh circuitry, the refresh circuitry for refreshing the DRAM cells of the second array;
a second external output, the second external output providing a second refresh request indication, wherein the second refresh request indication is indicative of a request to execute a refresh cycle of the second array based upon a measured temperature of the second temperature sensor.
9. The electronic system of claim 8 wherein the refresh request indication is carried on a first line and the second refresh request indication is carried on a second line, wherein the first line and the second line are hard wired together in a wired OR configuration.
10. An integrated circuit die including:
an array of dynamic random access memory (DRAM) cells;
a temperature sensor;
control circuitry;
refresh circuitry, the refresh circuitry for refreshing DRAM cells of the array;
refresh determination circuitry operably coupled to the temperature sensor, the refresh determination circuitry for generating requests to initiate a refresh cycle to refresh the array based upon a measured temperature of the temperature sensor; and
an external output, the external output providing a refresh request indication externally from the integrated circuit die, wherein the refresh request indication is indicative of a request to execute the refresh cycle of the array based upon the measured temperature of the temperature sensor.
11. The integrated circuit die of claim 10 further comprising:
a timer, wherein the refresh request indication is provided to indicate a refresh request based upon the timer.
12. The integrated circuit die of claim 10 wherein a rate of providing the refresh request indication to request a refresh request is based upon a measured temperature of the temperature sensor.
13. The integrated circuit die of claim 10 wherein the external output includes an external terminal, and wherein the refresh request indication includes a discrete signal asserted in a first state indicative of a request to execute a refresh cycle, the discrete signal having a second state indicative of no request to execute a refresh cycle.
14. The integrated circuit die of claim 10 wherein during a self refresh mode of operation, the control circuitry initiates self refresh cycles of the array by the refresh circuitry.
15. The integrated circuit die of claim 10 wherein during an active mode of operation, the external output provides the refresh request indication to indicate a request to execute a refresh cycle of the array, wherein the external output provides the refresh request indication to indicate a request to execute a refresh cycle of the array based upon a measured temperature of the temperature sensor.
16. The integrated circuit die of claim 15 wherein during a self refresh mode of operation, the external output does not provide the refresh request indication to request an execution of a refresh cycle.
17. The integrated circuit die of claim 15 wherein data read accesses and data write accesses can be made to the array during the active mode and data read accesses and data write accesses can not be made to the array during the self refresh mode.
18. The integrated circuit die of claim 15 wherein during the active mode, refresh cycles of the array are initiated by control circuitry located external to the die.
19. The electronic system of claim 3 wherein data read accesses and data write accesses can be made to the array during the active mode and data read accesses and data write accesses can not be made to the array during the self refresh mode.