Wireless communication device, integrated circuit and method of timing synchronisation
View Patent ↗A wireless communication device comprises a first sub-system arranged to pass data to a second sub-system comprising timing synchronization logic operably coupled to a counter, such that data is sampled by the timing synchronization logic when passed to the second sub-system from the first sub-system wherein the wireless communication device is characterized in that the timing synchronization logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system. In this manner, the inventive concept provides the wireless communication device with a mechanism to achieve timing synchronization. In particular, the inventive concept may allow a radio frequency integrated circuit to implement timing synchronization by advancing or retarding an ‘actual’ signal sent from digital baseband circuits in a 3G DigRF wireless communication device.
1. A wireless communication device comprises:
a first sub-system arranged to pass data to a second sub-system comprising timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the second sub-system from the first sub-system wherein the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine the position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system.
2. The wireless communication device of claim 1 wherein the timing synchronisation logic is arranged to determine a position of a synchronisation word for a frame of data being passed to the second sub-system.
3. The wireless communication device of claim 1 wherein the count value from the counting process is indicative of a time between successive data frames being passed to the second sub-system.
4. The wireless communication device of claim 1 wherein the timing synchronisation logic compares the count value from the counting process to at least one threshold value and determines whether to initiate a timing advance or timing retard operation in response to the comparison.
5. The wireless communication device of claim 4 wherein the at least one threshold is based on a clock period associated with the data being passed to the second sub-system.
6. The wireless communication device of claim 4 wherein the at least one threshold is based on a clock period that is not associated with the data being passed to the second sub-system.
7. The wireless communication device of claim 4 wherein at least two threshold levels are applied, a first threshold level identifying whether an advance operation should be initiated and a second threshold level identifying whether a retard operation should be initiated.
8. The wireless communication device of claim 7 wherein the first and second threshold levels define an acceptable timing margin either side of a desired counter value that is based on a clock period associated with the data being passed to the second sub-system.
9. The wireless communication device of claim 1 wherein the second sub-system is a radio frequency integrated circuit compliant with the 3G DigRF standard.
10. An integrated circuit for a wireless communication device comprising:
a sub-system and timing synchronisation logic operably coupled to a counter, such that data is sampled by the timing synchronisation logic when passed to the sub-system wherein the integrated circuit wherein the timing synchronisation logic is arranged to determine a position of a first data frame and in response thereto initiate a counting process of the counter and determine a position of a second data frame and in response thereto determine a count value from the counting process of the counter and in response to the count value determine whether to initiate a timing advance or timing retard operation on the data being passed to the sub-system.
11. The integrated circuit of claim 10 wherein the timing synchronisation logic is arranged to determine a position of a synchronisation word for a frame of data being passed to the sub-system.
12. The integrated circuit of claim 10 wherein the count value from the counting process is indicative of a time between successive data frames being passed to the at least one sub-system.
13. The integrated circuit of claim 10 wherein the timing synchronisation logic compares the value from the counting process to at least one threshold value and determines whether to initiate a timing advance or timing retard operation in response to the comparison.
14. The integrated circuit of claim 13 wherein the at least one threshold is based on a clock period associated with the data being passed to the sub-system.
15. The integrated circuit of claim 13 wherein the at least one threshold is based on a clock period that is not associated with the data being passed to the second sub-system.
16. The integrated circuit of claim 13 wherein at least two threshold levels are applied, a first threshold level identifying whether an advance operation should be initiated and a second threshold level identifying whether a retard operation should be initiated.
17. The integrated circuit of claim 15 wherein the first and second threshold levels define an acceptable timing margin either side of a desired counter value that is based on a clock period associated with the data being passed to the sub-system.
18. The integrated circuit of claim 10 where the integrated circuit is a radio frequency integrated circuit compliant with the 3G DigRF standard.
19. A method of synchronisation for a wireless communication device comprising:
passing data from a first sub-system to a second sub-system;
sampling the data;
determining a position of a first data frame from the sampled data;
initiating a counting process in response to determining a start of a first data frame;
determining a position of a second data frame;
determining a count value from the counting process in response thereto;
determining whether to initiate a timing advance or timing retard operation on the data being passed to the second sub-system in response to the count value.
20. A storage medium storing processor-implementable instructions for controlling a signal processor to carry out the method of claim 19 .