Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integration
View Patent ↗A method is provided for making a silicided gate ( 209 ). In accordance with the method, a semiconductor structure ( 201 ) is provided which comprises a semiconductor substrate ( 202 ), a gate ( 209 ) disposed on the semiconductor substrate, and a spacer ( 219 ) adjacent to the gate. The structure is subjected to a first etch which exposes a first lateral portion of the gate. An implant ( 215 ) is then created in a region adjacent to the spacer. The structure is then subjected to a second etch which exposes a second lateral portion of the gate electrode, and a layer of silicide ( 225 ) is formed which extends over the first and second lateral portions of the gate.
1. A method for making a silicided gate structure, comprising:
providing a semiconductor substrate having a gate disposed thereon and having a spacer disposed adjacent to the gate;
subjecting the spacer to a first etch which exposes a first lateral portion of the gate;
creating an implant region adjacent to the spacer after the first etch;
subjecting the spacer to a second etch which exposes a second lateral portion of the gate; and
forming a layer of silicide over the first and second lateral portions of the gate.
2. The method of claim 1 , wherein the layer of silicide also extends over a portion of the substrate adjacent to the spacer structure.
3. The method of claim 1 , wherein the layer of silicide is formed by depositing a conformal layer of a refractory metal such that the conformal layer is in contact with the first and second lateral portions of the gate.
4. The method of claim 3 , wherein the refractory metal is selected from the group consisting of Co, Ti, Ni, W, Pt and Pd.
5. The method of claim 1 , wherein the layer of silicide comprises a material selected from the group consisting of cobalt silicide, titanium silicide, nickel silicide, tungsten silicide, platinum silicide and palladium silicide.
6. The method of claim 1 , wherein the gate has a dielectric layer disposed thereon which separates the spacer from the gate, and wherein the second etch removes any exposed portion of the dielectric layer.
7. The method of claim 6 , wherein the step of creating an implant region adjacent to the spacer involves implanting a dopant into a substrate adjacent to the spacer, and wherein the implantation is aligned with the spacer.
8. The method of claim 7 , wherein the device has first and second implant regions in the substrate, wherein the second implant region is formed by an implantation that is aligned with the spacer prior to the second etch, and wherein the first implant region is formed by an implantation that is aligned with the gate.
9. The method of claim 8 , wherein the second implantation is not aligned with the spacer after the second etch.
10. The method of claim 8 , wherein the second etch reduces the width of the spacer.
11. The method of claim 8 , wherein said first and second implant regions form the source and drain regions of a transistor.
12. The method of claim 8 , wherein the first and second implant regions are each formed by implantation of a dopant followed by diffusion.
13. The method of claim 1 , wherein the first etch is selective to the material of the spacer.
14. The method of claim 13 , wherein a dielectric layer is disposed between the spacer and the gate electrode, and wherein the first etch also etches the dielectric layer.
15. The method of claim 1 wherein, prior to the first etch, the spacer covers the entire side of the electrode.
16. A method for making a silicided gate structure, comprising:
providing a semiconductor substrate having a gate disposed thereon;
depositing a conformal layer of spacer material over the gale;
etching the conformal layer to define first and second spacer structures therein, wherein the first and second spacer structures are adjacent to the gate;
subjecting the structure to a second etch which exposes a first lateral portion of the gate;
creating first and second implant regions adjacent to the first and second spacers after the second etch;
subjecting the structure to a third etch which exposes a second lateral portion of the gate; and
forming a layer of silicide over the first and second lateral portions of the gate.
17. The method of claim 16 , wherein the layer of silicide also extends over a portion of the substrate adjacent to the first and second spacer structures.
18. The method of claim 16 , wherein the layer of silicide is formed by depositing a conformal layer of a refractory metal such that the conformal layer is in contact with the first and second lateral portions of the gate.
19. The method of claim 18 , wherein the refractory metal is selected from the group consisting of Co, Ti, Ni, W, Pt and Pd.
20. The method of claim 16 , wherein the layer of silicide comprises cobalt silicide, titanium silicide, nickel silicide, tungsten silicide, platinum silicide and palladium silicide.
21. A method for making a silicided gate structure, comprising:
providing a semiconductor substrate having a gate disposed thereon and having a spacer disposed adjacent to the gate;
subjecting the spacer to a first etch which exposes a first portion of the sidewall of the gate;
creating an implant region adjacent to the spacer after the first etch;
subjecting the spacer to a second etch which exposes a second portion of the sidewall of the gate; and
forming a layer of silicide over the first and second portions of the gate.