IP Library Granted Patent US 7,456,679
Granted Patent B2
US 7,456,679 · App. 11/416,273 · Granted Nov 25, 2008

Reference circuit and method for generating a reference signal from a reference circuit

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Quick Facts
Patent No.
US 7,456,679
App. No.
11/416,273
Granted
Nov 25, 2008
Kind
B2
Abstract

A reference circuit includes: (a) a first reference circuit having a reference signal and a ΔV BE loop; and (b) a modification circuit using a first voltage to change a first current in the ΔV BE loop of the first reference circuit. In one embodiment, the reference circuit is a voltage reference circuit. In some embodiments, the reference circuit can include a bandgap core circuit, which adds a V BE and a multiplied ΔV BE , so that the output voltage of the reference circuit is a bandgap voltage. The reference circuit also can also include a modification circuit, which uses the output voltage (i.e. the reference signal) of the bandgap core circuit to change a current in the ΔV BE loop. The ΔV BE loop can be the portion of the circuit involved in generating the ΔV BE voltage. Other embodiments are disclosed in this application.

Claims (81)

1. A reference circuit comprising:

a first reference circuit having a first node for providing a reference signal and a ΔV BE loop; and

a modification circuit using a first voltage to change a first current in the ΔV BE loop of the first reference circuit,

where:

the change in the first current in the ΔV BE loop of the first reference circuit changes the reference signal to a modified reference signal;

V

mod

V

Bandgap

(

1

+

R

2

R

3

)

where V mod modified reference signal, V Bandgap is the reference signal of the first reference circuit without the modification circuit present, R 2 is a resistance value of a resistor in the first reference circuit, and R 3 is a resistance value of a resistor in the modification circuit; and

the modification circuit is electrically coupled in a path between the first node and the ΔV BE loop of the first reference circuit.

2. The reference circuit of claim 1 , wherein:

the modification circuit subtracts a second current from the first current in the ΔV BE loop of the first reference circuit to modify the reference signal of the first reference circuit.

3. The reference circuit of claim 2 , wherein:

the second current is a substantially fixed current, derived from the first voltage.

4. The reference circuit of claim 1 , wherein:

the modification circuit adds a second current to the first current in the ΔV BE loop of the first reference circuit to modify the reference signal of the first reference circuit.

5. The reference circuit of claim 4 , wherein:

the second current is a substantially fixed current, derived from the first voltage.

6. The reference circuit of claim 1 , wherein:

the modification circuit comprises a resistor electrically coupled between the first node and the ΔV BE loop of the first reference circuit.

7. The reference circuit of claim 6 , further comprising:

a switch to permit electrical disconnection of the resistor from ΔV BE loop of the first reference circuit.

8. The reference circuit of claim 1 , further comprising:

a disconnection circuit electrically coupled to the first reference circuit to permit electrical disconnection of the modification circuit front the ΔV BE loop of first reference circuit.

9. The reference circuit of claim 1 , wherein:

the modification circuit subtracts a substantially fixed second voltage from a first voltage in the ΔV BE loop of the first reference circuit to change the first current in the ΔV BE loop of the first reference circuit.

10. The reference circuit of claim 1 , wherein:

the modified reference signal is substantially independent of temperature and an input voltage to the first reference circuit.

11. The reference circuit of claim 1 , wherein the modified reference signal is lower than a voltage of a bandgap voltage of silicon.

12. The reference circuit of claim 1 , wherein the first reference circuit is a portion of Widlar bandgap circuit.

13. The reference circuit of claim 1 , wherein:

the reference circuit is characterized as a voltage reference circuit.

14. The reference circuit of claim 1 , wherein:

the reference circuit is characterized as a current reference circuit.

15. The reference circuit of claim 1 , wherein:

the first reference circuit comprises a bandgap core circuit.

16. A circuit for generating a reference voltage comprising:

a bandgap core circuit having an output voltage and a ΔV BE loop;

a modification circuit using the output voltage of the bandgap core circuit to change a first current in the ΔV BE loop of the bandgap core circuit and to change the output voltage to a modified output voltage,

wherein:

V

mod

V

Bandgap

(

1

+

R

2

R

3

)

where V mod is tie modified output voltage, V Bandgap is the output voltage of the bandgap core circuit without the modification circuit present, R 2 is a resistance value of a resistor in the bandgap core circuit and R 3 is a resistance value of a resistor in the modification circuit.

17. The reference circuit of claim 16 , wherein:

the modification circuit subtracts a second current from the first current in the ΔV BE loop of the bandgap core circuit to modify the output voltage of the bandgap core circuit.

18. The reference circuit of claim 17 , wherein:

the second current is a substantially fixed current, derived from the output voltage.

19. The reference circuit of claim 16 , wherein:

the modification circuit adds a second current to the first current in the ΔV BE loop of the bandgap core circuit to modify the output voltage of the bandgap core circuit.

20. The reference circuit of claim 19 , wherein:

the second current is a substantially fixed current, derived from the output voltage.

21. The reference circuit of claim 16 , wherein:

the modification circuit comprises a resistor electrically coupled between a first node of the bandgap core circuit and the ΔV BE loop of the bandgap core circuit.

22. The reference circuit of claim 21 , further comprising:

a switch to permit electrical disconnection of the resistor from ΔV BE loop of the bandgap core circuit.

23. The reference circuit of claim 16 , further comprising:

a disconnection circuit electrically coupled to the bandgap core circuit to permit electrical disconnection of the modification circuit from the ΔV BE loop of the bandgap core circuit.

24. The reference circuit of claim 16 , wherein:

the modified output voltage is substantially independent of temperature and an input voltage to the bandgap core circuit.

25. The reference circuit of claim 16 , wherein the modified output voltage is lower than a voltage of a bandgap voltage of silicon.

Assignments (32)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
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From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
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From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
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CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR INC.
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To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
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To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
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